[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Add GPIOs layout for Lewisburg PCH

[Maxim Polyakov (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/35031

to look at the new patch set (#15).

Change subject: soc/intel/skylake: Add GPIOs layout for Lewisburg PCH
......................................................................

soc/intel/skylake: Add GPIOs layout for Lewisburg PCH

The pin layout in this patch corresponds to the driver in the Linux
kernel for Lewisburg PCH GPIO hardware [1]

[1] drivers/pinctrl/intel/pinctrl-lewisburg.c

These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
    (PCH) Datasheet, May 2019. Document Number: 336067-007US

Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e
Signed-off-by: Maxim Polyakov 
---
M src/soc/intel/skylake/Kconfig
M src/soc/intel/skylake/Makefile.inc
M src/soc/intel/skylake/acpi/gpio.asl
M src/soc/intel/skylake/bootblock/pch.c
M src/soc/intel/skylake/gpio.c
M src/soc/intel/skylake/include/soc/gpio_defs.h
A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h
M src/soc/intel/skylake/include/soc/pcr_ids.h
8 files changed, 488 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/15