Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30998 )
Change subject: soc/amd/stoneyridge/gpio: Allow specifying 0 value for debounce timeout ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/gpio.h:
https://review.coreboot.org/#/c/30998/1/src/soc/amd/stoneyridge/include/soc/... PS1, Line 465: #define GPIO_IN_DEBOUNCE_DISABLED (0 | GPIO_TIMEBASE_61uS)
I think it would be clearer if it was just 0.
We do it both ways in plenty of places in the coreboot code. It's like (1 << 0) to match other shifts. I'm going to give it a +2 and let Dan decide whether to change it or not.