Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37781 )
Change subject: soc/intel/tigerlake: Update ACPI files ......................................................................
soc/intel/tigerlake: Update ACPI files
Add and update ACPI files for tiger lake SoC.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board
Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com Change-Id: Ib82156830273c2937f5f02713ed7dd27da41c857 --- M src/soc/intel/tigerlake/acpi/northbridge.asl A src/soc/intel/tigerlake/acpi/norththbridge.asl A src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl M src/soc/intel/tigerlake/acpi/pci_irqs.asl M src/soc/intel/tigerlake/acpi/pcie.asl M src/soc/intel/tigerlake/acpi/platform.asl A src/soc/intel/tigerlake/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/serialio.asl A src/soc/intel/tigerlake/acpi/sleepstates.asl A src/soc/intel/tigerlake/acpi/smbus.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 11 files changed, 937 insertions(+), 163 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/37781/1
diff --git a/src/soc/intel/tigerlake/acpi/northbridge.asl b/src/soc/intel/tigerlake/acpi/northbridge.asl index d6c2d34..399e28c 100644 --- a/src/soc/intel/tigerlake/acpi/northbridge.asl +++ b/src/soc/intel/tigerlake/acpi/northbridge.asl @@ -63,154 +63,154 @@ } }
+Name (MCRS, ResourceTemplate () +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) +}) + Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate () - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, - EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000) - - /* OPROM reserved (0xc0000-0xc3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc4000-0xc7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xc8000-0xcbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xcc000-0xcffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd0000-0xd3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd4000-0xd7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xd8000-0xdbfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000) - - /* OPROM reserved (0xdc000-0xdffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe0000-0xe3fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe4000-0xe7fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xe8000-0xebfff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000) - - /* BIOS Extension (0xec000-0xeffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000) - - /* System BIOS (0xf0000-0xfffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000) - - /* PCI Memory Region (TLUD - 0xdfffffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, - 0xE0000000,,, PM01) - - /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - - /* PCH reserved resource (0xfc800000-0xfe7fffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, - 0x00000000, PCH_PRESERVED_BASE_SIZE) - - /* TPM Area (0xfed40000-0xfed47fff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, - 0x00008000) - }) - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, PM01._MIN, PMIN) - CreateDwordField (MCRS, PM01._MAX, PMAX) - CreateDwordField (MCRS, PM01._LEN, PLEN) + CreateDwordField (^MCRS, ^PM01._MIN, PMIN) + CreateDwordField (^MCRS, ^PM01._MAX, PMAX) + CreateDwordField (^MCRS, ^PM01._LEN, PLEN)
/* * Fix up PCI memory region * Start with Top of Lower Usable DRAM */ - Store (_SB.PCI0.MCHC.TLUD, PMIN) + Store (^MCHC.TLUD, PMIN) Add (Subtract (PMAX, PMIN), 1, PLEN)
/* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, PM02._MIN, MMIN) - CreateQwordField (MCRS, PM02._MAX, MMAX) - CreateQwordField (MCRS, PM02._LEN, MLEN) + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN)
- Store (_SB.PCI0.MCHC.TUUD, Local0) + Store (^MCHC.TUUD, Local0)
If (LLessEqual (Local0, BASE_32GB)) { Store (BASE_32GB, MMIN) @@ -221,12 +221,9 @@ } Subtract (Add (MMIN, MLEN), 1, MMAX)
- Return (MCRS) + Return (^MCRS) }
-/* - * TODO: Clean up below functions and follow ASL2.0 code syntax - */ Name (EP_B, 0) /* to store EP BAR */ Name (MH_B, 0) /* to store MCH BAR */ Name (PC_B, 0) /* to store PCIe BAR */ @@ -310,11 +307,11 @@ */ Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE)
- /* Memory mapped SPI Flash range */ - Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000) + /* FLASH range */ + Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH)
/* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ - Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000) + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH)
/* HPET address decode range */ Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) diff --git a/src/soc/intel/tigerlake/acpi/norththbridge.asl b/src/soc/intel/tigerlake/acpi/norththbridge.asl new file mode 100644 index 0000000..399e28c --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/norththbridge.asl @@ -0,0 +1,339 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define BASE_32GB 0x800000000 +#define SIZE_16GB 0x400000000 + +Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID +Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID +Name (_SEG, Zero) // _SEG: PCI Segment +Name (_UID, Zero) // _UID: Unique ID + +Device (MCHC) +{ + Name (_ADR, 0x00000000) + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x40), /* EPBAR (0:0:0:40) */ + EPEN, 1, /* Enable */ + , 11, + EPBR, 20, /* EPBAR [31:12] */ + + Offset(0x48), /* MCHBAR (0:0:0:48) */ + MHEN, 1, /* Enable */ + , 14, + MHBR, 17, /* MCHBAR [31:15] */ + + Offset(0x60), /* PCIEXBAR (0:0:0:60) */ + PXEN, 1, /* Enable */ + PXSZ, 2, /* PCI Express Size */ + , 23, + PXBR, 6, /* PCI Express BAR [31:26] */ + + Offset(0x68), /* DMIBAR (0:0:0:68) */ + DIEN, 1, /* Enable */ + , 11, + DIBR, 20, /* DMIBAR [31:12] */ + + Offset (0xa0), /* Top of Used Memory */ + TOM, 64, + + Offset (0xa8), /* Top of Upper Used Memory */ + TUUD, 64, + + Offset (0xbc), /* Top of Low Used Memory */ + TLUD, 32, + } +} + +Name (MCRS, ResourceTemplate () +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, + EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + + /* PCI Memory Region (TLUD - 0xdfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0xdfffffff, 0x00000000, + 0xE0000000,,, PM01) + + /* PCI Memory Region (TUUD - (TUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) + + /* PCH reserved resource (0xfc800000-0xfe7fffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff, + 0x00000000, PCH_PRESERVED_BASE_SIZE) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) +}) + +Method (_CRS, 0, Serialized) +{ + /* Find PCI resource area in MCRS */ + CreateDwordField (^MCRS, ^PM01._MIN, PMIN) + CreateDwordField (^MCRS, ^PM01._MAX, PMAX) + CreateDwordField (^MCRS, ^PM01._LEN, PLEN) + + /* + * Fix up PCI memory region + * Start with Top of Lower Usable DRAM + */ + Store (^MCHC.TLUD, PMIN) + Add (Subtract (PMAX, PMIN), 1, PLEN) + + /* Patch PM02 range based on Memory Size */ + CreateQwordField (^MCRS, ^PM02._MIN, MMIN) + CreateQwordField (^MCRS, ^PM02._MAX, MMAX) + CreateQwordField (^MCRS, ^PM02._LEN, MLEN) + + Store (^MCHC.TUUD, Local0) + + If (LLessEqual (Local0, BASE_32GB)) { + Store (BASE_32GB, MMIN) + Store (SIZE_16GB, MLEN) + } Else { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (^MCRS) +} + +Name (EP_B, 0) /* to store EP BAR */ +Name (MH_B, 0) /* to store MCH BAR */ +Name (PC_B, 0) /* to store PCIe BAR */ +Name (PC_L, 0) /* to store PCIe BAR Length */ +Name (DM_B, 0) /* to store DMI BAR */ + +/* Get MCH BAR */ +Method (GMHB, 0, Serialized) +{ + If (LEqual (MH_B, 0)) { + ShiftLeft (_SB.PCI0.MCHC.MHBR, 15, MH_B) + } + Return (MH_B) +} + +/* Get EP BAR */ +Method (GEPB, 0, Serialized) +{ + If (LEqual (EP_B, 0)) { + ShiftLeft (_SB.PCI0.MCHC.EPBR, 12, EP_B) + } + Return (EP_B) +} + +/* Get PCIe BAR */ +Method (GPCB, 0, Serialized) +{ + If (LEqual (PC_B, 0)) { + ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, PC_B) + } + Return (PC_B) +} + +/* Get PCIe Length */ +Method (GPCL, 0, Serialized) +{ + If (LEqual (PC_L, 0)) { + ShiftRight (0x10000000, _SB.PCI0.MCHC.PXSZ, PC_L) + } + Return (PC_L) +} + +/* Get DMI BAR */ +Method (GDMB, 0, Serialized) +{ + If (LEqual (DM_B, 0)) { + ShiftLeft (_SB.PCI0.MCHC.DIBR, 12, DM_B) + } + Return (DM_B) +} + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 1) + + Name (BUF0, ResourceTemplate () + { + /* MCH BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.48h + */ + Memory32Fixed (ReadWrite, 0, 0x08000, MCHB) + + /* DMI BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.68h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, DMIB) + + /* EP BAR _BAS will be updated in _CRS below according to + * B0:D0:F0:Reg.40h + */ + Memory32Fixed (ReadWrite, 0, 0x01000, EGPB) + + /* PCI Express BAR _BAS and _LEN will be updated in + * _CRS below according to B0:D0:F0:Reg.60h + */ + Memory32Fixed (ReadWrite, 0, 0, PCIX) + + /* VTD engine memory range. + */ + Memory32Fixed (ReadOnly, VTD_BASE_ADDRESS, VTD_BASE_SIZE) + + /* FLASH range */ + Memory32Fixed (ReadOnly, 0xFFF00000, 0x1000000, FIOH) + + /* Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF) */ + Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000, LIOH) + + /* HPET address decode range */ + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + + Method (_CRS, 0, Serialized) + { + CreateDwordField (BUF0, ^MCHB._BAS, MBR0) + Store (_SB.PCI0.GMHB (), MBR0) + + CreateDwordField (BUF0, ^DMIB._BAS, DBR0) + Store (_SB.PCI0.GDMB (), DBR0) + + CreateDwordField (BUF0, ^EGPB._BAS, EBR0) + Store (_SB.PCI0.GEPB (), EBR0) + + CreateDwordField (BUF0, ^PCIX._BAS, XBR0) + Store (_SB.PCI0.GPCB (), XBR0) + + CreateDwordField (BUF0, ^PCIX._LEN, XSZ0) + Store (_SB.PCI0.GPCL (), XSZ0) + + Return (BUF0) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl b/src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl new file mode 100644 index 0000000..853bbb4 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define R_ICLK_PCR_CAMERA1 0x8000 +#define B_ICLK_PCR_FREQUENCY 0x1 +#define B_ICLK_PCR_REQUEST 0x2 + +Scope (_SB) { + Name (SBRG, 0xFD000000) + Name (ICKP, 0xAD) + + // IsCLK PCH register for clock settings + OperationRegion (ICLK, SystemMemory, Add(SBRG, Add(ShiftLeft(ICKP, 16), R_ICLK_PCR_CAMERA1)), 0x40) + Field(ICLK,AnyAcc,Lock,Preserve) + { + CLK1, 8, + Offset(0x0C), + CLK2, 8, + Offset(0x18), + CLK3, 8, + Offset(0x24), + CLK4, 8, + Offset(0x30), + CLK5, 8, + Offset(0x3C), + CLK6, 8, + } + + // + // Number Of Clocks + // + Method(NCLK, 0x0, NotSerialized) + { + Return (6) // IMGCLKOUT_0, IMGCLKOUT_1, IMGCLKOUT_2, IMGCLKOUT_3, IMGCLKOUT_4, IMGCLKOUT_5 + } + + + // + // Clock Control + // + Method(CLKC, 0x2, NotSerialized) + { + // + // Arg0 - Clock number (0:IMGCLKOUT_0, etc) + // Arg1 - Desired state (0:Disable, 1:Enable) + // + Switch(ToInteger(Arg0)) + { + Case (0) + { + Store(CLK1, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK1) + } + Case (1) + { + Store(CLK2, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK2) + } + Case (2) + { + Store(CLK3, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK3) + } + Case (3) + { + Store(CLK4, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK4) + } + Case (4) + { + Store(CLK5, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK5) + } + Case (5) + { + Store(CLK6, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_REQUEST)), ShiftLeft(Arg1, 1)), CLK6) + } + } + } + + // + // Clock Frequency + // + Method(CLKF, 0x2, NotSerialized) + { + // + // Arg0 - Clock number (0:IMGCLKOUT_0, etc) + // Arg1 - Clock frequency (0:24MHz, 1:19.2MHz) + // + Switch(ToInteger(Arg0)) + { + Case (0) + { + Store(CLK1, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK1) + } + Case (1) + { + Store(CLK2, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK2) + } + Case (2) + { + Store(CLK3, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK3) + } + Case (3) + { + Store(CLK4, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK4) + } + Case (4) + { + Store(CLK5, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK5) + } + Case (5) + { + Store(CLK6, Local0) + Store(Or(And(Local0, Not(B_ICLK_PCR_FREQUENCY)), Arg1), CLK6) + } + } + } + +//---------------------------------------------------------------------------------------- +// Clock control Method +// Arg0: Clock source select (0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3, 4: IMGCLKOUT_4) +// Arg1: Clock Enable / Disable (0: Disable, 1: Enable) +// Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz +//--------------------------------------------------------------------------------------- + Method(MCCT, 0x3, NotSerialized) + { + CLKC(ToInteger(Arg0),ToInteger(Arg1)) + CLKF(ToInteger(Arg0),ToInteger(Arg2)) + } +} diff --git a/src/soc/intel/tigerlake/acpi/pci_irqs.asl b/src/soc/intel/tigerlake/acpi/pci_irqs.asl index 19a3c12..594cad0 100644 --- a/src/soc/intel/tigerlake/acpi/pci_irqs.asl +++ b/src/soc/intel/tigerlake/acpi/pci_irqs.asl @@ -19,10 +19,10 @@ Name (PICP, Package () { /* PCI Bridge */ /* cAVS, SMBus, GbE, Nothpeak */ - Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ }, - Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ }, - Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ }, - Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ }, + Package(){0x001FFFFF, 0, 0, eSPI_IRQ }, + Package(){0x001FFFFF, 1, 0, P2SB_IRQ }, + Package(){0x001FFFFF, 2, 0, PMC_IRQ }, + Package(){0x001FFFFF, 3, 0, HDA_IRQ }, /* SerialIo and SCS */ Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ }, Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ }, @@ -38,8 +38,6 @@ Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ }, Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ }, Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ }, - /* eMMC */ - Package(){0x001AFFFF, 0, 0, eMMC_IRQ }, /* SerialIo */ Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ }, Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ }, @@ -56,15 +54,27 @@ Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ }, Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ }, Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ }, - /* D20: xHCI, OTG, SRAM, CNVi WiFi */ - Package(){0x0014FFFF, 0, 0, XHCI_IRQ }, - Package(){0x0014FFFF, 1, 0, OTG_IRQ }, + /* D20: xHCI, xDCI, SRAM, CNVi WiFi */ + Package(){0x0014FFFF, 0, 0, xHCI_IRQ }, + Package(){0x0014FFFF, 1, 0, xDCI_IRQ }, Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ }, Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ }, - /* Integrated Sensor Hub */ - Package(){0x0013FFFF, 0, 0, ISH_IRQ }, - /* Thermal */ - Package(){0x0012FFFF, 0, 0, THERMAL_IRQ }, + /* Serial IO */ + Package(){0x0013FFFF, 0, 0, LPSS_SPI3_IRQ }, + Package(){0x0013FFFF, 1, 0, LPSS_SPI4_IRQ }, + Package(){0x0013FFFF, 2, 0, LPSS_SPI5_IRQ }, + Package(){0x0013FFFF, 3, 0, LPSS_SPI6_IRQ }, + /* ISH */ + Package(){0x0012FFFF, 0, 0, ISH_IRQ }, + /* Serial IO */ + Package(){0x0011FFFF, 0, 0, LPSS_UART3_IRQ }, + Package(){0x0011FFFF, 1, 0, LPSS_UART4_IRQ }, + Package(){0x0011FFFF, 2, 0, LPSS_UART5_IRQ }, + Package(){0x0011FFFF, 3, 0, LPSS_UART6_IRQ }, + /* Serial IO/CNViBT */ + Package(){0x0010FFFF, 0, 0, LPSS_I2C6_IRQ }, + Package(){0x0010FFFF, 1, 0, LPSS_I2C7_IRQ }, + Package(){0x0010FFFF, 2, 0, CNViBT_IRQ }, /* Host Bridge */ /* Root Port D1F0 */ Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ }, @@ -79,6 +89,14 @@ Package(){0x0005FFFF, 0, 0, IPU_IRQ }, /* SA GNA Device */ Package(){0x0008FFFF, 0, 0, GNA_IRQ }, + /* TBT PCIE */ + Package(){0x0007FFFF, 0, 0, TBT_PCIe0_IRQ }, + Package(){0x0007FFFF, 1, 0, TBT_PCIe1_IRQ }, + Package(){0x0007FFFF, 2, 0, TBT_PCIe2_IRQ }, + Package(){0x0007FFFF, 3, 0, TBT_PCIe3_IRQ }, + /* USB2 Devices */ + Package(){0x000DFFFF, 0, 0, USB2_xHCI_IRQ }, + Package(){0x000DFFFF, 1, 0, USB2_xDCI_IRQ }, })
Name (PICN, Package () { diff --git a/src/soc/intel/tigerlake/acpi/pcie.asl b/src/soc/intel/tigerlake/acpi/pcie.asl index 0191454..092ac57 100644 --- a/src/soc/intel/tigerlake/acpi/pcie.asl +++ b/src/soc/intel/tigerlake/acpi/pcie.asl @@ -380,3 +380,71 @@ Return (IRQM (RPPN)) } } + +Device (TBT1) +{ + Name (_ADR, 0x001D0008) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (TBT2) +{ + Name (_ADR, 0x001D0009) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (TBT3) +{ + Name (_ADR, 0x001D000A) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} + +Device (TBT4) +{ + Name (_ADR, 0x001D000B) + + OperationRegion (RPCS, PCI_Config, 0x4c, 4) + Field (RPCS, AnyAcc, NoLock, Preserve) + { + , 24, + RPPN, 8, /* Root Port Number */ + } + + Method (_PRT) + { + Return (IRQM (RPPN)) + } +} diff --git a/src/soc/intel/tigerlake/acpi/platform.asl b/src/soc/intel/tigerlake/acpi/platform.asl index dde9b13..3c9e24e 100644 --- a/src/soc/intel/tigerlake/acpi/platform.asl +++ b/src/soc/intel/tigerlake/acpi/platform.asl @@ -18,6 +18,15 @@ /* Generic indicator for sleep state */ #include <soc/intel/common/acpi/platform.asl>
+/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + /* * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. diff --git a/src/soc/intel/tigerlake/acpi/pmc.asl b/src/soc/intel/tigerlake/acpi/pmc.asl new file mode 100644 index 0000000..fa31836 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/pmc.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +// Intel PMC Controller 0:1f.2 + +#include <soc/iomap.h> + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, PCH_PWRM_BASE_ADDRESS, 0x10000, IBAR) + IO (Decode16, ACPI_BASE_ADDRESS, 0x1880, 0x04,0x80) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + 0x12 + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } +} diff --git a/src/soc/intel/tigerlake/acpi/serialio.asl b/src/soc/intel/tigerlake/acpi/serialio.asl index 0b0e3da..461b04a 100644 --- a/src/soc/intel/tigerlake/acpi/serialio.asl +++ b/src/soc/intel/tigerlake/acpi/serialio.asl @@ -19,70 +19,177 @@ { Name (_ADR, 0x00150000) Name (_DDN, "Serial IO I2C Controller 0") + Method (_PS0) { } + Method (_PS3) { } }
Device (I2C1) { Name (_ADR, 0x00150001) Name (_DDN, "Serial IO I2C Controller 1") + Method (_PS0) { } + Method (_PS3) { } }
Device (I2C2) { Name (_ADR, 0x00150002) Name (_DDN, "Serial IO I2C Controller 2") + Method (_PS0) { } + Method (_PS3) { } }
Device (I2C3) { Name (_ADR, 0x00150003) Name (_DDN, "Serial IO I2C Controller 3") + Method (_PS0) { } + Method (_PS3) { } }
Device (I2C4) { Name (_ADR, 0x00190000) Name (_DDN, "Serial IO I2C Controller 4") + Method (_PS0) { } + Method (_PS3) { } }
Device (I2C5) { Name (_ADR, 0x00190001) Name (_DDN, "Serial IO I2C Controller 5") + Method (_PS0) { } + Method (_PS3) { } }
+Device (I2C6) +{ + Name (_ADR, 0x00100000) + Name (_DDN, "Serial IO I2C Controller 6") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (I2C7) +{ + Name (_ADR, 0x00100001) + Name (_DDN, "Serial IO I2C Controller 7") + Method (_PS0) { } + Method (_PS3) { } +} + + Device (SPI0) { Name (_ADR, 0x001e0002) Name (_DDN, "Serial IO SPI Controller 0") + Method (_PS0) { } + Method (_PS3) { } }
Device (SPI1) { Name (_ADR, 0x001e0003) Name (_DDN, "Serial IO SPI Controller 1") + Method (_PS0) { } + Method (_PS3) { } }
Device (SPI2) { Name (_ADR, 0x00120006) Name (_DDN, "Serial IO SPI Controller 2") + Method (_PS0) { } + Method (_PS3) { } }
+Device (SPI3) +{ + Name (_ADR, 0x00130000) + Name (_DDN, "Serial IO SPI Controller 3") + Method (_PS0) { } + Method (_PS3) { } +} + + +Device (SPI4) +{ + Name (_ADR, 0x00130001) + Name (_DDN, "Serial IO SPI Controller 4") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (SPI5) +{ + Name (_ADR, 0x00130002) + Name (_DDN, "Serial IO SPI Controller 5") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (SPI6) +{ + Name (_ADR, 0x00130003) + Name (_DDN, "Serial IO SPI Controller 6") + Method (_PS0) { } + Method (_PS3) { } +} + + Device (UAR0) { Name (_ADR, 0x001e0000) Name (_DDN, "Serial IO UART Controller 0") + Method (_PS0) { } + Method (_PS3) { } }
Device (UAR1) { Name (_ADR, 0x001e0001) Name (_DDN, "Serial IO UART Controller 1") + Method (_PS0) { } + Method (_PS3) { } }
Device (UAR2) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (UAR3) +{ + Name (_ADR, 0x00110000) + Name (_DDN, "Serial IO UART Controller 3") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (UAR4) +{ + Name (_ADR, 0x00110001) + Name (_DDN, "Serial IO UART Controller 4") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (UAR5) +{ + Name (_ADR, 0x00110002) + Name (_DDN, "Serial IO UART Controller 5") + Method (_PS0) { } + Method (_PS3) { } +} + +Device (UAR6) +{ + Name (_ADR, 0x00110003) + Name (_DDN, "Serial IO UART Controller 6") + Method (_PS0) { } + Method (_PS3) { } } diff --git a/src/soc/intel/tigerlake/acpi/sleepstates.asl b/src/soc/intel/tigerlake/acpi/sleepstates.asl new file mode 100644 index 0000000..7958f30 --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/sleepstates.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name (_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) +Name (_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) +Name (_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) diff --git a/src/soc/intel/tigerlake/acpi/smbus.asl b/src/soc/intel/tigerlake/acpi/smbus.asl new file mode 100644 index 0000000..a15622b --- /dev/null +++ b/src/soc/intel/tigerlake/acpi/smbus.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Intel SMBus Controller 0:1f.4 + +Device (SBUS) +{ + Name (_ADR, 0x001f0004) +} diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 7de8ac4..d15696e 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -1,7 +1,8 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2017-2019 Intel Corp. + * (Written by Bora Guvendik bora.guvendik@intel.com for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,15 +20,16 @@ #include <soc/itss.h> #include <soc/pcr_ids.h>
+ /* PCI IRQ assignment */ #include "pci_irqs.asl"
+/* PCH clock */ +#include "pch_clock_ctl.asl" + /* PCR access */ #include <soc/intel/common/acpi/pcr.asl>
-/* eMMC, SD Card */ -#include "scs.asl" - /* GPIO controller */ #include "gpio.asl"
@@ -40,14 +42,17 @@ /* PCIE Ports */ #include "pcie.asl"
+/* pmc 0:1f.2 */ +#include "pmc.asl" + /* Serial IO */ #include "serialio.asl"
+/* SMBus 0:1f.4 */ +#include "smbus.asl" + /* USB XHCI 0:14.0 */ #include "xhci.asl"
/* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> - -/* GBe 0:1f.6 */ -#include "pch_glan.asl"