Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/51395 )
Change subject: soc/amd: move warm reset flag function prototypes to common code ......................................................................
soc/amd: move warm reset flag function prototypes to common code
Even though the implementation is different on Stoneyridge compared to Picasso and Cezanne, the function prototypes are identical, so move them to the AMD SoC common reset header file.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957 --- M src/soc/amd/cezanne/cpu.c D src/soc/amd/cezanne/include/soc/reset.h M src/soc/amd/cezanne/reset.c M src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/picasso/cpu.c D src/soc/amd/picasso/include/soc/reset.h M src/soc/amd/picasso/mca.c M src/soc/amd/picasso/reset.c M src/soc/amd/stoneyridge/cpu.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/mca.c 11 files changed, 7 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/51395/1
diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 6754bba..148dcd8 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h> +#include <amdblocks/reset.h> #include <amdblocks/smm.h> #include <console/console.h> #include <cpu/amd/microcode.h> @@ -12,7 +13,6 @@ #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> -#include <soc/reset.h>
/* MP and SMM loading initialization */
diff --git a/src/soc/amd/cezanne/include/soc/reset.h b/src/soc/amd/cezanne/include/soc/reset.h deleted file mode 100644 index 4cb94ce..0000000 --- a/src/soc/amd/cezanne/include/soc/reset.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_CEZANNE_RESET_H -#define AMD_CEZANNE_RESET_H - -void set_warm_reset_flag(void); -int is_warm_reset(void); - -#endif /* AMD_CEZANNE_RESET_H */ diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c index 89b5b80..aae76bf 100644 --- a/src/soc/amd/cezanne/reset.c +++ b/src/soc/amd/cezanne/reset.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <cf9_reset.h> #include <reset.h> -#include <soc/reset.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index b825f47..353720c 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -9,6 +9,8 @@
void do_warm_reset(void); void do_cold_reset(void); +void set_warm_reset_flag(void); +int is_warm_reset(void);
static inline __noreturn void warm_reset(void) { diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 088660e..36bbf0a 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h> +#include <amdblocks/reset.h> #include <amdblocks/smm.h> #include <cpu/cpu.h> #include <cpu/x86/mp.h> @@ -12,7 +13,6 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/cpu.h> -#include <soc/reset.h> #include <soc/smi.h> #include <soc/iomap.h> #include <console/console.h> diff --git a/src/soc/amd/picasso/include/soc/reset.h b/src/soc/amd/picasso/include/soc/reset.h deleted file mode 100644 index fb47068..0000000 --- a/src/soc/amd/picasso/include/soc/reset.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef AMD_PICASSO_RESET_H -#define AMD_PICASSO_RESET_H - -void set_warm_reset_flag(void); -int is_warm_reset(void); - -#endif /* AMD_PICASSO_RESET_H */ diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index e16d0a1..c21f4f1 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/reset.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> -#include <soc/reset.h> #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c index 89b5b80..aae76bf 100644 --- a/src/soc/amd/picasso/reset.c +++ b/src/soc/amd/picasso/reset.c @@ -3,7 +3,6 @@ #include <arch/io.h> #include <cf9_reset.h> #include <reset.h> -#include <soc/reset.h> #include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/reset.h> diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index d943deb..e007637 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/reset.h> #include <amdblocks/smm.h> #include <cpu/amd/msr.h> #include <cpu/cpu.h> diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h index d00f566..8eb3a25 100644 --- a/src/soc/amd/stoneyridge/include/soc/northbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h @@ -86,7 +86,5 @@ void domain_enable_resources(struct device *dev); void domain_read_resources(struct device *dev); void fam15_finalize(void *chip_info); -void set_warm_reset_flag(void); -int is_warm_reset(void);
#endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */ diff --git a/src/soc/amd/stoneyridge/mca.c b/src/soc/amd/stoneyridge/mca.c index 0f2900c..b1f955f 100644 --- a/src/soc/amd/stoneyridge/mca.c +++ b/src/soc/amd/stoneyridge/mca.c @@ -1,9 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <amdblocks/reset.h> #include <cpu/x86/msr.h> #include <acpi/acpi.h> #include <soc/cpu.h> -#include <soc/northbridge.h> #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h>