Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33624 )
Change subject: soc/amd/stoneyridge: Change code to accommodate merlinfalcon SOC ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl File src/soc/amd/stoneyridge/acpi/cpu.asl:
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/acpi/cpu.asl... PS3, Line 37: If (LGreaterEqual (\PCNT, 8)) I kind of thought 2 CUs, i.e. 4 cores was the max for Models 60-6F. Are you just trying to cover all possible bases here, or do you know of a MF that has 8 cores?
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/include/soc/... File src/soc/amd/stoneyridge/include/soc/pci_devs.h:
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/include/soc/... PS3, Line 44: * Device IDs For the record, I'm OK with not #define-ing the device IDs here. BTW, it's a shame we don't use the Gfx IDs in the detection used for the vbios.
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/northbridge.... File src/soc/amd/stoneyridge/northbridge.c:
https://review.coreboot.org/#/c/33624/3/src/soc/amd/stoneyridge/northbridge.... PS3, Line 351: Can you remove these tabs so that it matches the nearby source? I thought you said you'd change it. Maybe it's your editor did it automatically?