Dolan Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86328?usp=email )
Change subject: fatcat: Add 64M fmd file ......................................................................
fatcat: Add 64M fmd file
add 64MiB size rom support on fatcat only add size to 64M and no others flashmap change
Change-Id: I7df35f89c7a42e92bba66a292722ef7a3374c4fd --- M src/mainboard/google/fatcat/Kconfig A src/mainboard/google/fatcat/chromeos-64M.fmd 2 files changed, 54 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/86328/1
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index e82081d..a67ea3b 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -3,16 +3,14 @@ config BOARD_GOOGLE_FATCAT_COMMON def_bool n select BOARD_ROMSIZE_KB_32768 - select DRIVERS_GFX_GENERIC select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID - select DRIVERS_INTEL_DPTF select DRIVERS_INTEL_MIPI_CAMERA select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_WWAN_FM350GL select DRIVERS_AUDIO_SOF - select DRIVERS_SOUNDWIRE_ALC_BASE_7XX + select DRIVERS_SOUNDWIRE_ALC722 select DRIVERS_SPI_ACPI select DUMP_SMBIOS_TYPE17 select EC_ACPI @@ -33,7 +31,6 @@ select MAINBOARD_HAS_TPM2 select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE - select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD select SOC_INTEL_PANTHERLAKE_U_H @@ -44,7 +41,6 @@ select BOARD_GOOGLE_FATCAT_COMMON select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_INTEL_ISH - select DRIVER_INTEL_ISH_HAS_MAIN_FW select DRIVERS_INTEL_USB4_RETIMER select HAVE_SLP_S0_GATE select MAINBOARD_HAS_CHROMEOS @@ -58,7 +54,6 @@ config BOARD_GOOGLE_MODEL_FATCAT def_bool n select BOARD_GOOGLE_BASEBOARD_FATCAT - select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENERIC_MAX98357A
config BOARD_GOOGLE_FATCAT @@ -118,7 +113,10 @@ hex default 0x03 if BOARD_GOOGLE_MODEL_FATCAT default 0x01 if BOARD_GOOGLE_FRANCKA - default 0x01 if BOARD_GOOGLE_FELINO + +config FMDFILE + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if CHROMEOS
config HAVE_SLP_S0_GATE def_bool n diff --git a/src/mainboard/google/fatcat/chromeos-64M.fmd b/src/mainboard/google/fatcat/chromeos-64M.fmd new file mode 100644 index 0000000..1e43dad --- /dev/null +++ b/src/mainboard/google/fatcat/chromeos-64M.fmd @@ -0,0 +1,49 @@ +FLASH 64M { + SI_ALL 8M { + SI_DESC 16K + SI_ME + } + SI_BIOS 24M { + RW_SECTION_A 8M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + RW_MISC 1M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + RW_LEGACY(CBFS) 1M + RW_UNUSED 2M + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO 4M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +}