[coreboot-gerrit] Change in coreboot[master]: soc/intel/braswell,skylake: Drop logo parameters from devicetree

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50361 )

Change subject: soc/intel/braswell,skylake: Drop logo parameters from devicetree
......................................................................

soc/intel/braswell,skylake: Drop logo parameters from devicetree

We can never pass memory location of dynamically loaded BMP files in
the static devicetree. The parameters passed to FSP are filled runtime.

Change-Id: Ib835ec0d9349ec96d5635e228063f2b7000b70fd
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/chip.h
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
4 files changed, 0 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/50361/1

diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index d759602..af274ac 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -120,8 +120,6 @@
    params->PcdPchUsbHsicPort		= config->PcdPchUsbHsicPort;
    params->PcdPcieRootPortSpeed		= 0;
    params->PcdPchSsicEnable		= config->PcdPchSsicEnable;
-	params->PcdLogoPtr			= config->PcdLogoPtr;
-	params->PcdLogoSize			= config->PcdLogoSize;
    params->PcdRtcLock			= 0;
    params->PMIC_I2CBus			= config->PMIC_I2CBus;
    params->ISPEnable			= config->ISPEnable;
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index c27ee49..732d73b 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -131,8 +131,6 @@
    uint8_t  PcdPchUsbSsicPort;
    uint8_t  PcdPchUsbHsicPort;
    uint8_t  PcdPchSsicEnable;
-	uint32_t PcdLogoPtr;
-	uint32_t PcdLogoSize;
    uint8_t  PMIC_I2CBus;
    uint8_t  ISPEnable;
    uint8_t  ISPPciDevConfig;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 5b05dd2..88f432d 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -256,9 +256,6 @@
    dev = pcidev_path_on_root(PCH_DEVFN_CSE_3);
    params->Heci3Enabled = dev && dev->enabled;

-	params->LogoPtr = config->LogoPtr;
-	params->LogoSize = config->LogoSize;
-
    params->CpuConfig.Bits.VmxEnable = CONFIG(ENABLE_VMX);

params->PchPmWoWlanEnable = config->PchPmWoWlanEnable;
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e5592b4..bef0f12 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -288,14 +288,6 @@
    u8 SkipExtGfxScan;
    u8 ScanExtGfxForLegacyOpRom;

-	/*
-	 * The following fields come from fsp_vpd.h
-	 * These are configuration values that are passed to FSP during
-	 * SiliconInit.
-	 */
-	u32 LogoPtr;
-	u32 LogoSize;
-
    /* GPIO IRQ Route  The valid values is 14 or 15*/
    u8 GpioIrqSelect;
    /* SCI IRQ Select  The valid values is 9, 10, 11 and 20 21, 22, 23*/