Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36777 )
Change subject: cpu/x86/lapic: Cleanup code ......................................................................
cpu/x86/lapic: Cleanup code
* Don't use long as it compiles to 64bit on x86_64, which breaks interrupts in qemu and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code
Tested on Qemu Q35 with x86_64 enabled: Interrupts working again. Tested on Qemu Q35 with x86_32 enabled: Interrupts are still working.
Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph siro@das-labor.org --- M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 3 files changed, 18 insertions(+), 57 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36777/1
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 755fbe2..6eb72f9 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -58,6 +58,6 @@ LAPIC_DELIVERY_MODE_NMI) );
- printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid()); + printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid()); printk(BIOS_INFO, "done.\n"); } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e7dfc57..1e5c96a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -101,7 +101,7 @@ static int lapic_start_cpu(unsigned long apicid) { int timeout; - unsigned long send_status, accept_status; + uint32_t send_status, accept_status; int j, maxlvt;
/* @@ -133,11 +133,11 @@ printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " "Disabling\n", apicid); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } return 0; @@ -230,7 +230,7 @@ if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) - printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + printk(BIOS_WARNING, "APIC delivery error (%x).\n", accept_status); if (send_status || accept_status) return 0; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6fd1997..8800ad2 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -6,14 +6,14 @@ #include <halt.h> #include <smp/node.h>
-static __always_inline unsigned long lapic_read(unsigned long reg) +static __always_inline uint32_t lapic_read(unsigned long reg) { - return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); + return *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)); }
-static __always_inline void lapic_write(unsigned long reg, unsigned long v) +static __always_inline void lapic_write(unsigned long reg, uint32_t v) { - *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; + *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)) = v; }
static __always_inline void lapic_wait_icr_idle(void) @@ -40,7 +40,7 @@ wrmsr(LAPIC_BASE_MSR, msr); }
-static __always_inline unsigned long lapicid(void) +static __always_inline uint32_t lapicid(void) { return lapic_read(LAPIC_ID) >> 24; } @@ -58,58 +58,19 @@ void stop_this_cpu(void); #endif
-#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ - sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* - * Note: no "lock" prefix even on SMP: xchg always implies lock anyway - * Note 2: xchg has side effect, so that attribute volatile is necessary, - * but generally the primitive is invalid, *ptr is output argument. --ANK - */ -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) +static inline void lapic_write_atomic(unsigned long reg, volatile uint32_t v) { - switch (size) { - case 1: - __asm__ __volatile__("xchgb %b0,%1" - : "=q" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 2: - __asm__ __volatile__("xchgw %w0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 4: - __asm__ __volatile__("xchgl %0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - } - return x; + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg); + + asm volatile ("xchgl %0, %1\n" + : "+r" (v), "+m" (*(ptr)) + : : "memory", "cc"); }
-static inline void lapic_write_atomic(unsigned long reg, unsigned long v) -{ - (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); -} - - -#ifdef X86_GOOD_APIC -# define FORCE_READ_AROUND_WRITE 0 -# define lapic_read_around(x) lapic_read(x) -# define lapic_write_around(x, y) lapic_write((x), (y)) -#else -# define FORCE_READ_AROUND_WRITE 1 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -#endif
void do_lapic_init(void);