Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34875 )
Change subject: cpu,soc/intel/smm: Define inlined smm_lock() ......................................................................
cpu,soc/intel/smm: Define inlined smm_lock()
Change-Id: I66983b771feb5c05744255b9000c742c4c0e5025 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/smmrelocate.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smi.c 30 files changed, 101 insertions(+), 172 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34875/1
diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1eb6f68..e2f468d 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -332,14 +332,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index b0c2c1a..b32af6f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -34,11 +34,6 @@
#define SMRR_SUPPORTED (1 << 11)
-#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
@@ -141,17 +136,6 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); }
-void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fc..12247ab 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -23,11 +23,24 @@ } __packed;
/* These helpers are for performing SMM relocation. */ -void northbridge_write_smram(u8 smram); - -void smm_lock(void); void smm_relocate(void);
+#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +static inline void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + nb_smram_lock(); +} + /* The initialization of the southbridge is split into 2 components. One is * for clearing the state in the SMM registers. The other is for enabling * SMIs. They are split so that other work between the 2 actions. */ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 7033f89..e6ccdb6 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" @@ -35,12 +36,10 @@ return (void *)tolm; }
-void northbridge_write_smram(u8 smram); - -void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); - pci_write_config8(mch, SMRAMC, smram); + pci_write_config8(mch, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); }
void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7eb07b8..207b120 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -124,6 +124,12 @@ return (void *) top_of_ram; }
+void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 384d98a..39f98da 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -219,16 +219,6 @@ return NULL; }
-void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 59508be..a81a4bb 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -41,6 +41,12 @@ return (void *)smm_region_start(); }
+void nb_smram_lock(void) +{ + pci_devfn_t dev = PCI_DEV(0,0,0); + pci_write_config8(dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = smm_region_start(); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 3d3457d..93b307c 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -90,6 +90,12 @@ return ggc2uma[gms] << 10; }
+void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dd4e8ac..73de993 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -154,16 +154,6 @@ return NULL; }
-void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852..ea99da7 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -21,7 +21,8 @@
#include <cpu/intel/smm_reloc.h>
-void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_devfn_t qpd_d0f1 = PCI_DEV(QUICKPATH_BUS, 0, 1); + pci_write_config8(qpd_d0f1, QPD0F1_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2400c59..fd02f77 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -140,6 +140,12 @@
}
+void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 34cb583..b8dbaa2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -140,16 +140,6 @@ add_fixed_resources(dev, index); }
-void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 41330f2..368456b 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -48,6 +48,12 @@ return CONFIG_SMM_TSEG_SIZE; }
+void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 58f4a68..a5872b6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,11 +444,6 @@ MCHBAR32(0x5500) = 0x00100001; }
-void northbridge_write_smram(u8 smram) -{ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); -} - static struct pci_operations intel_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 42786bb..b802973 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -135,6 +135,12 @@ return (void *) top_of_ram; }
+void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ee70527..8b5b9e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -171,16 +171,6 @@ return NULL; }
-void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0e..062963d 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -56,3 +56,8 @@ *start = tseg; *size = bgsm - tseg; } + +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 21c534a..13d591d 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -295,14 +295,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 276b9a3..15ca276 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -35,6 +35,11 @@ *size = sa_get_tseg_size(); }
+void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 493d003..11fe760 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -254,15 +254,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 0d41f25..94b1daf 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -33,6 +33,11 @@ *size = sa_get_tseg_size(); }
+void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 65505c4..bb77375 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9d3f377..e4f4487 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -36,6 +36,11 @@ *size = sa_get_tseg_size(); }
+void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..479abf7 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index ac53ae1..678d5d7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -37,9 +37,6 @@ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif - -void aseg_smm_lock(void); - #endif
#define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 94d8e14..422ed57 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -304,7 +304,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER)) - aseg_smm_lock(); + smm_lock(); }
static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 521b98d..d85cd63 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -27,16 +27,6 @@ #include <string.h> #include "i82801dx.h"
- -void northbridge_write_smram(u8 smram); - -/* For intel/e7505. */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -343,16 +333,6 @@ restore_default_smm_area(default_smm_area); }
-void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* The GDT or coreboot table is going to live here. But a long time diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 31eabb6..421a101 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -212,8 +212,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID))
-void aseg_smm_lock(void); - #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ba2b028..cb79e96 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -431,7 +431,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER) && CONFIG(SMM_ASEG)) - aseg_smm_lock(); + smm_lock(); }
static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 0a80dd2..c02e823 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -30,6 +30,7 @@ #include "i82801ix.h"
/* I945/GM45 */ + #define SMRAM 0x9d #define D_OPEN (1 << 6) #define D_CLS (1 << 5) @@ -126,6 +127,24 @@
static int smm_handler_copied = 0;
+static void nb_smram_open(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); +} + +static void nb_smram_close(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, G_SMRAME | C_BASE_SEG); +} + +void nb_smram_lock(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -135,24 +154,20 @@ return; smm_handler_copied = 1;
- /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */
if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); + nb_smram_open();
/* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, _binary_smm_end - _binary_smm_start); wbinvd(); } - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - G_SMRAME | C_BASE_SEG); + nb_smram_close(); }
void smm_init(void) @@ -171,14 +186,3 @@ { restore_default_smm_area(default_smm_area); } - -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -}