Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11761
-gerrit
commit 06db1d7ad83744b43e5b9b8f2a6675de4c62a3e3 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Wed Sep 30 20:23:09 2015 -0700
WIP: cpu/mtrr.h: Fix macro names for MTRR registers
The names are pathetic.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/cpu/amd/agesa/s3_resume.c | 2 +- src/cpu/amd/car/cache_as_ram.inc | 38 ++++++++++---------- src/cpu/amd/car/disable_cache_as_ram.c | 10 +++--- src/cpu/amd/model_fxx/model_fxx_init.c | 6 ++-- src/cpu/amd/pi/s3_resume.c | 2 +- src/cpu/amd/smm/smm_init.c | 6 ++-- src/cpu/intel/car/cache_as_ram.inc | 42 +++++++++++------------ src/cpu/intel/car/cache_as_ram_ht.inc | 14 ++++---- src/cpu/intel/fsp_model_406dx/bootblock.c | 2 +- src/cpu/intel/haswell/bootblock.c | 6 ++-- src/cpu/intel/haswell/cache_as_ram.inc | 14 ++++---- src/cpu/intel/model_2065x/bootblock.c | 2 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 16 ++++----- src/cpu/intel/model_206ax/bootblock.c | 2 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 14 ++++---- src/cpu/intel/model_6ex/cache_as_ram.inc | 14 ++++---- src/cpu/via/car/cache_as_ram.inc | 34 +++++++++--------- src/cpu/x86/mp_init.c | 10 +++--- src/cpu/x86/mtrr/earlymtrr.c | 8 ++--- src/cpu/x86/mtrr/mtrr.c | 24 ++++++------- src/drivers/intel/fsp1_1/cache_as_ram.inc | 4 +-- src/include/cpu/x86/mtrr.h | 34 +++++++++--------- src/northbridge/intel/nehalem/raminit.c | 2 +- src/soc/intel/baytrail/bootblock/bootblock.c | 2 +- src/soc/intel/baytrail/romstage/cache_as_ram.inc | 14 ++++---- src/soc/intel/braswell/bootblock/bootblock.c | 2 +- src/soc/intel/broadwell/bootblock/cpu.c | 6 ++-- src/soc/intel/broadwell/romstage/cache_as_ram.inc | 14 ++++---- src/soc/intel/common/util.c | 36 +++++++++---------- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 2 +- src/soc/intel/skylake/bootblock/cpu.c | 6 ++-- 31 files changed, 194 insertions(+), 194 deletions(-)
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index 98671f4..5bec115 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -89,7 +89,7 @@ static void set_resume_cache(void) /* Set the default memory type and disable fixed and enable variable MTRRs */ msr.hi = 0; msr.lo = (1 << 11); - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache(); } diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 133daac..70a55c3 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -76,9 +76,9 @@ cache_as_ram_setup: cvtsd2si %xmm3, %ebx
/* Check if cpu_init_detected. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $MTRRdefTypeEn, %eax + andl $MTRR_DEF_TYPE_EN, %eax movl %eax, %ebx /* We store the status. */
jmp_if_k8(CAR_FAM10_out_post_errata) @@ -270,27 +270,27 @@ clear_fixed_var_mtrr_out:
#if CacheSize > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx simplemask CacheSize, 0x8000 wrmsr #endif
#if CacheSize > 0x10000 /* Enable caching for 64K-96K using fixed MTRR. */ - movl $MTRRfix4K_D0000_MSR, %ecx + movl $MTRR_FIX_4K_D0000, %ecx simplemask CacheSize, 0x10000 wrmsr #endif
#if CacheSize > 0x18000 /* Enable caching for 96K-128K using fixed MTRR. */ - movl $MTRRfix4K_D8000_MSR, %ecx + movl $MTRR_FIX_4K_D8000, %ecx simplemask CacheSize, 0x18000 wrmsr #endif
/* Enable caching for 0-32K using fixed MTRR. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx simplemask CacheSize, 0 wrmsr
@@ -326,9 +326,9 @@ wbcache_post_fam10_setup: #endif /* CONFIG_XIP_ROM_SIZE */
/* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr
/* Enable the MTRRs and IORRs in SYSCFG. */ @@ -462,17 +462,17 @@ cache_as_ram_switch_stack:
all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */ .long MTRRphysBase_MSR(0) diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c index d3a3812..3b464b8 100644 --- a/src/cpu/amd/car/disable_cache_as_ram.c +++ b/src/cpu/amd/car/disable_cache_as_ram.c @@ -33,15 +33,15 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
msr.lo = 0; msr.hi = 0; - wrmsr(MTRRfix4K_C8000_MSR, msr); + wrmsr(MTRR_FIX_4K_C8000, msr); #if CONFIG_DCACHE_RAM_SIZE > 0x8000 - wrmsr(MTRRfix4K_C0000_MSR, msr); + wrmsr(MTRR_FIX_4K_C0000, msr); #endif #if CONFIG_DCACHE_RAM_SIZE > 0x10000 - wrmsr(MTRRfix4K_D0000_MSR, msr); + wrmsr(MTRR_FIX_4K_D0000, msr); #endif #if CONFIG_DCACHE_RAM_SIZE > 0x18000 - wrmsr(MTRRfix4K_D8000_MSR, msr); + wrmsr(MTRR_FIX_4K_D8000, msr); #endif /* disable fixed mtrr from now on, it will be enabled by ramstage again*/
@@ -53,7 +53,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void) msr.hi = 0; msr.lo = (1 << 11);
- wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache(); } diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c b/src/cpu/amd/model_fxx/model_fxx_init.c index a6561ee..40325aa 100644 --- a/src/cpu/amd/model_fxx/model_fxx_init.c +++ b/src/cpu/amd/model_fxx/model_fxx_init.c @@ -110,7 +110,7 @@ static void save_mtrr_state(struct mtrr_state *state) } state->top_mem = rdmsr(TOP_MEM); state->top_mem2 = rdmsr(TOP_MEM2); - state->def_type = rdmsr(MTRRdefType_MSR); + state->def_type = rdmsr(MTRR_DEF_TYPE_MSR); }
static void restore_mtrr_state(struct mtrr_state *state) @@ -124,7 +124,7 @@ static void restore_mtrr_state(struct mtrr_state *state) } wrmsr(TOP_MEM, state->top_mem); wrmsr(TOP_MEM2, state->top_mem2); - wrmsr(MTRRdefType_MSR, state->def_type); + wrmsr(MTRR_DEF_TYPE_MSR, state->def_type);
enable_cache(); } @@ -173,7 +173,7 @@ static void set_init_ecc_mtrrs(void) /* Set the default type to write combining */ msr.hi = 0x00000000; msr.lo = 0xc00 | MTRR_TYPE_WRCOMB; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr);
/* Set TOP_MEM to 4G */ msr.hi = 0x00000001; diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c index 943fd97..59265fb 100644 --- a/src/cpu/amd/pi/s3_resume.c +++ b/src/cpu/amd/pi/s3_resume.c @@ -279,7 +279,7 @@ static void set_resume_cache(void) /* Set the default memory type and disable fixed and enable variable MTRRs */ msr.hi = 0; msr.lo = (1 << 11); - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr);
enable_cache(); } diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 2e9a4c9..e13f24f 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -39,7 +39,7 @@ void smm_init(void)
/* Back up MSRs for later restore */ syscfg_orig = rdmsr(SYSCFG_MSR); - mtrr_aseg_orig = rdmsr(MTRRfix16K_A0000_MSR); + mtrr_aseg_orig = rdmsr(MTRR_FIX_16K_A0000);
/* MTRR changes don't like an enabled cache */ disable_cache(); @@ -57,7 +57,7 @@ void smm_init(void) /* set DRAM access to 0xa0000 */ msr.lo = 0x18181818; msr.hi = 0x18181818; - wrmsr(MTRRfix16K_A0000_MSR, msr); + wrmsr(MTRR_FIX_16K_A0000, msr);
/* enable the extended features */ msr = syscfg_orig; @@ -73,7 +73,7 @@ void smm_init(void)
/* Restore SYSCFG and MTRR */ wrmsr(SYSCFG_MSR, syscfg_orig); - wrmsr(MTRRfix16K_A0000_MSR, mtrr_aseg_orig); + wrmsr(MTRR_FIX_16K_A0000, mtrr_aseg_orig); enable_cache();
/* CPU MSR are set in CPU init */ diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index f9be6e8..75a905b 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -54,7 +54,7 @@ CacheAsRam: */ xorl %eax, %eax xorl %edx, %edx - movl $MTRRfix64K_00000_MSR, %ecx + movl $MTRR_FIX_64K_00000, %ecx wrmsr
/* @@ -102,16 +102,16 @@ SIPI_Delay:
/* Wait for the Logical AP to complete initialization. */ LogicalAP_SIPINotdone: - movl $MTRRfix64K_00000_MSR, %ecx + movl $MTRR_FIX_64K_00000, %ecx rdmsr orl %eax, %eax jz LogicalAP_SIPINotdone
NotHtProcessor: /* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr
/* Clear all MTRRs. */ @@ -131,17 +131,17 @@ clear_fixed_var_mtrr:
all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */ .long MTRRphysBase_MSR(0) @@ -219,13 +219,13 @@ clear_fixed_var_mtrr_out:
#if CacheSize > 0x8000 /* Enable caching for 32K-64K using fixed MTRR. */ - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx simplemask CacheSize, 0x8000 wrmsr #endif
/* Enable caching for 0-32K using fixed MTRR. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx simplemask CacheSize, 0 wrmsr
@@ -332,13 +332,13 @@ lout: movl %eax, %cr0
/* Clear sth. */ - movl $MTRRfix4K_C8000_MSR, %ecx + movl $MTRR_FIX_4K_C8000, %ecx xorl %edx, %edx xorl %eax, %eax wrmsr
#if CONFIG_DCACHE_RAM_SIZE > 0x8000 - movl $MTRRfix4K_C0000_MSR, %ecx + movl $MTRR_FIX_4K_C0000, %ecx wrmsr #endif
@@ -346,9 +346,9 @@ lout: * Set the default memory type and disable fixed * and enable variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $MTRRdefTypeEn, %eax /* Enable variable and disable fixed MTRRs. */ + movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */ wrmsr
/* Enable cache. */ diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 193ad41..08d71cc 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -61,7 +61,7 @@ clear_mtrrs: post_code(0x21)
/* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -242,9 +242,9 @@ sipi_complete: wrmsr
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x2b) @@ -356,9 +356,9 @@ no_msr_11e: post_code(0x34)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x35) @@ -413,9 +413,9 @@ no_msr_11e: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index a685eaa..055c5c5 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -74,7 +74,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void set_no_evict_mode_msr(void) diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index f5d0f6c..3eb5439 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void set_flex_ratio_to_tdp_nominal(void) @@ -113,12 +113,12 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR);
/* Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); halt(); diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 0978bfb..153e221 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -73,7 +73,7 @@ clear_mtrrs:
post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -95,9 +95,9 @@ clear_mtrrs: post_code(0x25)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -197,9 +197,9 @@ before_romstage: post_code(0x31)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x31) @@ -279,9 +279,9 @@ before_romstage: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index b6a2442..fb83709 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -60,7 +60,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index cfa3b6b..4a384f5 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -48,8 +48,8 @@ wait_for_sipi: jc wait_for_sipi
post_code(0x21) - /* Clean-up MTRRdefType_MSR. */ - movl $MTRRdefType_MSR, %ecx + /* Clean-up MTRR_DEF_TYPE_MSR. */ + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %eax, %eax xorl %edx, %edx wrmsr @@ -100,9 +100,9 @@ clear_var_mtrrs: post_code(0x25)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -189,9 +189,9 @@ before_romstage: post_code(0x31)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x31) @@ -261,9 +261,9 @@ before_romstage: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index d41afb2..840f777 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index a3f1c64..9294c2d 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -68,7 +68,7 @@ clear_mtrrs:
post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -90,9 +90,9 @@ clear_mtrrs: post_code(0x25)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -189,9 +189,9 @@ before_romstage: post_code(0x31)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x31) @@ -269,9 +269,9 @@ before_romstage: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 271b756..f46014c 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -52,7 +52,7 @@ clear_mtrrs: jnz clear_mtrrs
/* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -70,9 +70,9 @@ clear_mtrrs: wrmsr
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
/* Enable L2 cache. */ @@ -150,9 +150,9 @@ clear_mtrrs: post_code(0x31)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x31) @@ -207,9 +207,9 @@ clear_mtrrs: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index e8a4ee2..fa715e1 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -44,9 +44,9 @@ CacheAsRam: invd
/* Set the default memory type and enable fixed and variable MTRRs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax + movl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax wrmsr
/* Clear all MTRRs. */ @@ -66,17 +66,17 @@ clear_fixed_var_mtrr:
all_mtrr_msrs: /* fixed MTRR MSRs */ - .long MTRRfix64K_00000_MSR - .long MTRRfix16K_80000_MSR - .long MTRRfix16K_A0000_MSR - .long MTRRfix4K_C0000_MSR - .long MTRRfix4K_C8000_MSR - .long MTRRfix4K_D0000_MSR - .long MTRRfix4K_D8000_MSR - .long MTRRfix4K_E0000_MSR - .long MTRRfix4K_E8000_MSR - .long MTRRfix4K_F0000_MSR - .long MTRRfix4K_F8000_MSR + .long MTRR_FIX_64K_00000 + .long MTRR_FIX_16K_80000 + .long MTRR_FIX_16K_A0000 + .long MTRR_FIX_4K_C0000 + .long MTRR_FIX_4K_C8000 + .long MTRR_FIX_4K_D0000 + .long MTRR_FIX_4K_D8000 + .long MTRR_FIX_4K_E0000 + .long MTRR_FIX_4K_E8000 + .long MTRR_FIX_4K_F0000 + .long MTRR_FIX_4K_F8000
/* var MTRR MSRs */ .long MTRRphysBase_MSR(0) @@ -132,9 +132,9 @@ clear_fixed_var_mtrr_out:
/* Set the default memory type and enable fixed and variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn), %eax + movl $(MTRR_DEF_TYPE_EN), %eax wrmsr
/* Enable cache. */ @@ -224,9 +224,9 @@ testok:
/* Set the default memory type and enable variable MTRRs. */ /* TODO: Or also enable fixed MTRRs? Bug in the code? */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx xorl %edx, %edx - movl $(MTRRdefTypeEn), %eax + movl $(MTRR_DEF_TYPE_EN), %eax wrmsr
/* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */ diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 3c8450f..ffac818 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -179,10 +179,10 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp)
#define NUM_FIXED_MTRRS 11 static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { - MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, - MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, - MTRRfix4K_D8000_MSR, MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, - MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, + MTRR_FIX_64K_00000, MTRR_FIX_16K_80000, MTRR_FIX_16K_A0000, + MTRR_FIX_4K_C0000, MTRR_FIX_4K_C8000, MTRR_FIX_4K_D0000, + MTRR_FIX_4K_D8000, MTRR_FIX_4K_E0000, MTRR_FIX_4K_E8000, + MTRR_FIX_4K_F0000, MTRR_FIX_4K_F8000, };
static inline struct saved_msr *save_msr(int index, struct saved_msr *entry) @@ -229,7 +229,7 @@ static int save_bsp_msrs(char *start, int size) msr_entry = save_msr(MTRRphysMask_MSR(i), msr_entry); }
- msr_entry = save_msr(MTRRdefType_MSR, msr_entry); + msr_entry = save_msr(MTRR_DEF_TYPE_MSR, msr_entry);
return msr_count; } diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 9561d8d..c2ae2ef 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -36,7 +36,7 @@ const int addr_det = 0; static void do_early_mtrr_init(const unsigned long *mtrr_msrs) { /* Precondition: - * The cache is not enabled in cr0 nor in MTRRdefType_MSR + * The cache is not enabled in cr0 nor in MTRR_DEF_TYPE_MSR * entry32.inc ensures the cache is not enabled in cr0 */ msr_t msr; @@ -65,7 +65,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
@@ -99,7 +99,7 @@ static inline int early_mtrr_init_detected(void) * on both Intel and AMD cpus, at least * according to the documentation. */ - msr = rdmsr(MTRRdefType_MSR); - return msr.lo & MTRRdefTypeEn; + msr = rdmsr(MTRR_DEF_TYPE_MSR); + return msr.lo & MTRR_DEF_TYPE_EN; } #endif diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 1994a56..154579e 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -81,19 +81,19 @@ void enable_fixed_mtrr(void) { msr_t msr;
- msr = rdmsr(MTRRdefType_MSR); - msr.lo |= MTRRdefTypeEn | MTRRdefTypeFixEn; - wrmsr(MTRRdefType_MSR, msr); + msr = rdmsr(MTRR_DEF_TYPE_MSR); + msr.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void enable_var_mtrr(unsigned char deftype) { msr_t msr;
- msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR); msr.lo &= ~0xff; - msr.lo |= MTRRdefTypeEn | deftype; - wrmsr(MTRRdefType_MSR, msr); + msr.lo |= MTRR_DEF_TYPE_EN | deftype; + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ @@ -250,11 +250,11 @@ static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; /* Fixed MTRR descriptors. */ static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { { PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000), - PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRRfix64K_00000_MSR }, + PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRR_FIX_64K_00000 }, { PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000), - PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRRfix16K_80000_MSR }, + PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRR_FIX_16K_80000 }, { PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000), - PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRRfix4K_C0000_MSR }, + PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRR_FIX_4K_C0000 }, };
static void calc_fixed_mtrrs(void) @@ -818,16 +818,16 @@ void x86_mtrr_check(void) msr_t msr; printk(BIOS_DEBUG, "\nMTRR check\n");
- msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR);
printk(BIOS_DEBUG, "Fixed MTRRs : "); - if (msr.lo & MTRRdefTypeFixEn) + if (msr.lo & MTRR_DEF_TYPE_FIX_EN) printk(BIOS_DEBUG, "Enabled\n"); else printk(BIOS_DEBUG, "Disabled\n");
printk(BIOS_DEBUG, "Variable MTRRs: "); - if (msr.lo & MTRRdefTypeEn) + if (msr.lo & MTRR_DEF_TYPE_EN) printk(BIOS_DEBUG, "Enabled\n"); else printk(BIOS_DEBUG, "Disabled\n"); diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index d4df67b..44df112 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -260,9 +260,9 @@ before_romstage: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bd0b603..8669eb1 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -18,11 +18,11 @@ #define MTRRcapFix (1 << 8) #define MTRRcapVcnt 0xff
-#define MTRRdefType_MSR 0x2ff +#define MTRR_DEF_TYPE_MSR 0x2ff +#define MTRR_DEF_TYPE_MASK 0xff +#define MTRR_DEF_TYPE_EN (1 << 11) +#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
-#define MTRRdefTypeEn (1 << 11) -#define MTRRdefTypeFixEn (1 << 10) -#define MTRRdefTypeType 0xff
#define SMRRphysBase_MSR 0x1f2 #define SMRRphysMask_MSR 0x1f3 @@ -32,19 +32,19 @@
#define MTRRphysMaskValid (1 << 11)
-#define NUM_FIXED_RANGES 88 -#define RANGES_PER_FIXED_MTRR 8 -#define MTRRfix64K_00000_MSR 0x250 -#define MTRRfix16K_80000_MSR 0x258 -#define MTRRfix16K_A0000_MSR 0x259 -#define MTRRfix4K_C0000_MSR 0x268 -#define MTRRfix4K_C8000_MSR 0x269 -#define MTRRfix4K_D0000_MSR 0x26a -#define MTRRfix4K_D8000_MSR 0x26b -#define MTRRfix4K_E0000_MSR 0x26c -#define MTRRfix4K_E8000_MSR 0x26d -#define MTRRfix4K_F0000_MSR 0x26e -#define MTRRfix4K_F8000_MSR 0x26f +#define NUM_FIXED_RANGES 88 +#define RANGES_PER_FIXED_MTRR 8 +#define MTRR_FIX_64K_00000 0x250 +#define MTRR_FIX_16K_80000 0x258 +#define MTRR_FIX_16K_A0000 0x259 +#define MTRR_FIX_4K_C0000 0x268 +#define MTRR_FIX_4K_C8000 0x269 +#define MTRR_FIX_4K_D0000 0x26a +#define MTRR_FIX_4K_D8000 0x26b +#define MTRR_FIX_4K_E0000 0x26c +#define MTRR_FIX_4K_E8000 0x26d +#define MTRR_FIX_4K_F0000 0x26e +#define MTRR_FIX_4K_F8000 0x26f
#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index c41310a..568cb14 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -2076,7 +2076,7 @@ static void enable_cache(unsigned int base, unsigned int size) msr.lo = base | MTRR_TYPE_WRPROT; msr.hi = 0; wrmsr(MTRRphysBase_MSR(3), msr); - msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRRdefTypeEn) + msr.lo = ((~(ALIGN_DOWN(size + 4096, 4096) - 1) | MTRR_DEF_TYPE_EN) & 0xffffffff); msr.hi = 0x0000000f; wrmsr(MTRRphysMask_MSR(3), msr); diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 6d31add..1c14e18 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -47,7 +47,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void setup_mmconfig(void) diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index 583ec58..cfb2959 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -60,7 +60,7 @@ wait_for_sipi: post_code(0x21) /* Configure the default memory type to uncacheable as well as disable * fixed and variable range mtrrs. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -120,9 +120,9 @@ wait_for_sipi: wrmsr
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x26) @@ -198,9 +198,9 @@ before_romstage: post_code(0x2c)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
invd @@ -258,9 +258,9 @@ before_romstage: post_code(0x30)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x31) diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index f98f694..68b5e97 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -48,7 +48,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void setup_mmconfig(void) diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 83bd873..cc6e2d3 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -54,7 +54,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void bootblock_mdelay(int ms) @@ -120,12 +120,12 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR);
/* Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) { + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { outb(0x0, 0xcf9); outb(0x6, 0xcf9); halt(); diff --git a/src/soc/intel/broadwell/romstage/cache_as_ram.inc b/src/soc/intel/broadwell/romstage/cache_as_ram.inc index 3f1b12a..297b0f1 100644 --- a/src/soc/intel/broadwell/romstage/cache_as_ram.inc +++ b/src/soc/intel/broadwell/romstage/cache_as_ram.inc @@ -76,7 +76,7 @@ clear_mtrrs:
post_code(0x22) /* Configure the default memory type to uncacheable. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr andl $(~0x00000cff), %eax wrmsr @@ -98,9 +98,9 @@ clear_mtrrs: post_code(0x25)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */ @@ -217,9 +217,9 @@ before_romstage: post_code(0x31)
/* Disable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - andl $(~MTRRdefTypeEn), %eax + andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
post_code(0x31) @@ -299,9 +299,9 @@ before_romstage: post_code(0x3a)
/* Enable MTRR. */ - movl $MTRRdefType_MSR, %ecx + movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr - orl $MTRRdefTypeEn, %eax + orl $MTRR_DEF_TYPE_EN, %eax wrmsr
post_code(0x3b) diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index a6adfaf..5376897 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -105,13 +105,13 @@ static void soc_display_mtrr_fixed_types(uint64_t msr, uint32_t next_type; uint32_t type;
- type = msr & MTRRdefTypeType; + type = msr & MTRR_DEF_TYPE_MASK; base_address = starting_address; next_address = base_address; for (index = 0; index < 64; index += 8) { next_address = starting_address + (memory_size * ((index >> 3) + 1)); - next_type = (msr >> index) & MTRRdefTypeType; + next_type = (msr >> index) & MTRR_DEF_TYPE_MASK; if (next_type != type) { printk(BIOS_DEBUG, " 0x%08x - 0x%08x: %s\n", base_address, next_address - 1, @@ -159,7 +159,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr;
- msr.s = rdmsr(MTRRfix64K_00000_MSR); + msr.s = rdmsr(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -187,12 +187,12 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr;
- msr.s = rdmsr(MTRRdefType_MSR); + msr.s = rdmsr(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, - (msr.u64 & MTRRdefTypeEn) ? " E," : "", - (msr.u64 & MTRRdefTypeFixEn) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & MTRRdefTypeType))); + (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", + (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", + soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); }
static void soc_display_variable_mtrr(uint32_t msr_reg, int index, @@ -218,7 +218,7 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, printk(BIOS_DEBUG, "0x%016llx: PHYBASE%d: Address = 0x%016llx, %s\n", msr_a.u64, index, base_address, - soc_display_mtrr_type(msr_a.u64 & MTRRdefTypeType)); + soc_display_mtrr_type(msr_a.u64 & MTRR_DEF_TYPE_MASK)); mask = (msr_m.u64 & 0xfffffffffffff000ULL) & address_mask; length = (~mask & address_mask) + 1; printk(BIOS_DEBUG, @@ -243,25 +243,25 @@ asmlinkage void soc_display_mtrrs(void) variable_mtrrs = soc_display_mtrrcap(); soc_display_mtrr_def_type(); soc_display_64k_mtrr(); - soc_display_16k_mtrr(MTRRfix16K_80000_MSR, 0x80000, + soc_display_16k_mtrr(MTRR_FIX_16K_80000, 0x80000, "IA32_MTRR_FIX16K_80000"); - soc_display_16k_mtrr(MTRRfix16K_A0000_MSR, 0xa0000, + soc_display_16k_mtrr(MTRR_FIX_16K_A0000, 0xa0000, "IA32_MTRR_FIX16K_A0000"); - soc_display_4k_mtrr(MTRRfix4K_C0000_MSR, 0xc0000, + soc_display_4k_mtrr(MTRR_FIX_4K_C0000, 0xc0000, "IA32_MTRR_FIX4K_C0000"); - soc_display_4k_mtrr(MTRRfix4K_C8000_MSR, 0xc8000, + soc_display_4k_mtrr(MTRR_FIX_4K_C8000, 0xc8000, "IA32_MTRR_FIX4K_C8000"); - soc_display_4k_mtrr(MTRRfix4K_D0000_MSR, 0xd0000, + soc_display_4k_mtrr(MTRR_FIX_4K_D0000, 0xd0000, "IA32_MTRR_FIX4K_D0000"); - soc_display_4k_mtrr(MTRRfix4K_D8000_MSR, 0xd8000, + soc_display_4k_mtrr(MTRR_FIX_4K_D8000, 0xd8000, "IA32_MTRR_FIX4K_D8000"); - soc_display_4k_mtrr(MTRRfix4K_E0000_MSR, 0xe0000, + soc_display_4k_mtrr(MTRR_FIX_4K_E0000, 0xe0000, "IA32_MTRR_FIX4K_E0000"); - soc_display_4k_mtrr(MTRRfix4K_E8000_MSR, 0xe8000, + soc_display_4k_mtrr(MTRR_FIX_4K_E8000, 0xe8000, "IA32_MTRR_FIX4K_E8000"); - soc_display_4k_mtrr(MTRRfix4K_F0000_MSR, 0xf0000, + soc_display_4k_mtrr(MTRR_FIX_4K_F0000, 0xf0000, "IA32_MTRR_FIX4K_F0000"); - soc_display_4k_mtrr(MTRRfix4K_F8000_MSR, 0xf8000, + soc_display_4k_mtrr(MTRR_FIX_4K_F8000, 0xf8000, "IA32_MTRR_FIX4K_F8000"); address_bits = cpu_phys_address_size(); address_mask = (1ULL << address_bits) - 1; diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 50d321b..8c93472 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -80,7 +80,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void setup_mmconfig(void) diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 6c5ab4f..42a8ab0 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -61,7 +61,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); }
static void bootblock_mdelay(int ms) @@ -167,14 +167,14 @@ static void set_flex_ratio_to_tdp_nominal(void) static void check_for_clean_reset(void) { msr_t msr; - msr = rdmsr(MTRRdefType_MSR); + msr = rdmsr(MTRR_DEF_TYPE_MSR);
/* * Use the MTRR default type MSR as a proxy for detecting INIT#. * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRRdefTypeEn | MTRRdefTypeFixEn)) + if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) soft_reset(); }