[coreboot-gerrit] Patch set updated for coreboot: abb0053 ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`

[Paul Menzel]

Paul Menzel ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2957

-gerrit

commit abb00534d1c801e00acbf8473b5ee5cc14e7b5e1
Author: Paul Menzel 
Date:   Fri Mar 29 15:39:54 2013 +0100

ASRock E350M1: mainboard.c: Include `cimx_util.h` for `pm_iowrite`

When building the ASRock E350M1, the following warning is shown.

$ make # on Jenkins (build server)
        […]
            CC         mainboard/asrock/e350m1/mainboard.ramstage.o
        src/mainboard/asrock/e350m1/mainboard.c: In function 'mainboard_enable':
        src/mainboard/asrock/e350m1/mainboard.c:63:2: warning: implicit declaration of function 'pm_iowrite' [-Wimplicit-function-declaration]
        […]

This warning was introduced by moving the initialization of the
    ASF registers using `pm_iowrite` to `mainboard.c` in

commit db6c5bfd8bdef4489e7fec533cb2ca8ae6c24cf3
        Author: Jens Rottmann 
        Date:   Thu Mar 21 22:21:28 2013 +0100

Asrock E350M1: Use SPD read code from F14 wrapper

Reviewed-on: http://review.coreboot.org/2875

and is fixed by including `southbridge/amd/cimx/cimx_util.h`
    declaring `pm_iowrite`.

Note, that the other AMD SB800 based boards seem to use the
    header file `southbridge/amd/sb800/sb800.h`, so no warning is shown
    for those. But since the CIMx SB800 code is used, the routines
    from the CIMx directory are more appropriate to declare these functions.

So delete the commented out include line for this header too.

Change-Id: I179aad5157c5a91294339a3e7b6c4c1715c6f099
    Signed-off-by: Paul Menzel 
---
 src/mainboard/asrock/e350m1/mainboard.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index be5c36c..a98a179 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -24,7 +24,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
-//#include <southbridge/amd/sb800/sb800.h>
+#include <southbridge/amd/cimx/cimx_util.h>

//#define SMBUS_IO_BASE 0x6000
 void set_pcie_reset(void);