[coreboot-gerrit] Change in coreboot[master]: soc/mediatek/mt8192: Get DDR base information after calibration

[CK HU (Code Review)]

Hello Duan huayang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44712

to review the following change.

Change subject: soc/mediatek/mt8192: Get DDR base information after calibration
......................................................................

soc/mediatek/mt8192: Get DDR base information after calibration

Signed-off-by: Huayang Duan 
Change-Id: Ie62948368716d309aab8149372b2b6093fc33552
---
M src/soc/mediatek/mt8192/dramc_pi_basic_api.c
M src/soc/mediatek/mt8192/dramc_pi_main.c
2 files changed, 83 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44712/1

diff --git a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
index adabb80..31e8d0e 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_basic_api.c
@@ -3835,6 +3835,36 @@
    	write32(regs_bak[i].addr, regs_bak[i].value);
 }

+u8 dramc_mode_reg_read(u8 chn, u8 mr_idx)
+{
+	u8 value;
+
+	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSMA, mr_idx);
+	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 1);
+
+	/* Wait until MRW command fired */
+	while (READ32_BITFIELD(&ch[chn].nao.spcmdresp, SPCMDRESP_MRR_RESPONSE) == 0)
+		udelay(1);
+
+	value = READ32_BITFIELD(&ch[chn].nao.mrr_status, MRR_STATUS_MRR_SW_REG);
+	SET32_BITFIELDS(&ch[chn].ao.swcmd_en, SWCMD_EN_MRREN, 0);
+	dramc_dbg("Read MR%d =%#x\n", mr_idx, value);
+
+	return value;
+}
+
+u8 dramc_mode_reg_read_by_rank(u8 chn, u8 rank, u8 mr_idx)
+{
+	u8 value = 0;
+	u8 rank_bak;
+
+	rank_bak = READ32_BITFIELD(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK);
+	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank);
+	value = dramc_mode_reg_read(chn, mr_idx);
+	SET32_BITFIELDS(&ch[chn].ao.swcmd_ctrl0, SWCMD_CTRL0_MRSRK, rank_bak);
+	return value;
+}
+
 void dramc_mode_reg_write_by_rank(const struct ddr_cali *cali,
    u8 chn, u8 rank, u8 mr_idx, u8 value)
 {
diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c
index 355cc9d..cf199dc 100644
--- a/src/soc/mediatek/mt8192/dramc_pi_main.c
+++ b/src/soc/mediatek/mt8192/dramc_pi_main.c
@@ -14,6 +14,55 @@
    mt6359p_buck_set_voltage(MT6359P_GPU11, vcore);
 }

+static void get_dram_info_after_cal(struct ddr_cali *cali)
+{
+	u8 vendor_id, density, max_density = 0;
+	u32 size_Gb, max_size = 0;
+
+	vendor_id = dramc_mode_reg_read_by_rank(CHANNEL_A, RANK_0, 5) & 0xff;
+	dramc_info("Vendor id is %#x\n", vendor_id);
+
+	for (u8 rk = RANK_0; rk < cali->support_ranks; rk++) {
+		density = dramc_mode_reg_read_by_rank(CHANNEL_A, rk, 8) & 0xff;
+		dramc_dbg("MR8 %#x\n", density);
+		density = (density >> 2) & 0xf;
+
+		switch (density) {
+		case 0x0:
+			size_Gb = 4;
+			break;
+		case 0x1:
+			size_Gb = 6;
+			break;
+		case 0x2:
+			size_Gb = 8;
+			break;
+		case 0x3:
+			size_Gb = 12;
+			break;
+		case 0x4:
+			size_Gb = 16;
+			break;
+		case 0x5:
+			size_Gb = 24;
+			break;
+		case 0x6:
+			size_Gb = 32;
+			break;
+		default:
+			size_Gb = 0;
+			break;
+		}
+		if (size_Gb > max_size) {
+			max_size = size_Gb;
+			max_density = density;
+		}
+		dramc_dbg("RK%d size %dGb, density:%d\n", rk, size_Gb, max_density);
+	}
+
+	cali->density = max_density;
+}
+
 static void dramc_calibration_all_channels(struct ddr_cali *cali)
 {
 }
@@ -91,6 +140,10 @@

dramc_calibration_all_channels(&cali);

+		/* only need do once for get DDR's base information */
+		if (first_freq_k)
+			get_dram_info_after_cal(&cali);
+
    	first_freq_k= false;
    }
 }