Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35678 )
Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset ......................................................................
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/early_init.c M src/southbridge/intel/i82801gx/i82801gx.h 4 files changed, 26 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/35678/1
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index cee7c2a..23f010c 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -15,7 +15,6 @@
#include <stdint.h> #include <cf9_reset.h> -#include <delay.h> #include <console/console.h> #include <arch/romstage.h> #include <cpu/x86/lapic.h> @@ -246,10 +245,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config_w83627thg(); diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 93b24a0..7949b69 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -17,7 +17,6 @@ #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> -#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -209,10 +208,8 @@
enable_lapic();
- /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_BUS_RESET); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0); + /* Force PCIRST# to cardbus add-on. */ + ich7_p2p_secondary_reset();
ich7_enable_lpc(); early_superio_config(); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d6d37d9..7ed58f6 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -17,6 +17,8 @@ #include <cf9_reset.h> #include <console/console.h> #include <arch/io.h> +#include <delay.h> +#include <device/pci.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cbmem.h> @@ -549,14 +551,9 @@ * PCI bus 0x0a and check whether we find a device on 0:a.0 */
- /* First we reset the secondary bus */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; /* SRESET */ - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
reg16 = pci_read_config16(p2peg, SLOTSTS); printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16); @@ -565,10 +562,7 @@ reg16 |= (1 << 4) | (1 << 0); pci_write_config16(p2peg, SLOTSTS, reg16);
- pci_write_config8(p2peg, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(p2peg, PCI_SECONDARY_BUS, tmp_secondary); - pci_write_config8(p2peg, PCI_SUBORDINATE_BUS, tmp_secondary); + pci_s_bridge_set_secondary(p2peg, tmp_secondary);
reg32 = pci_read_config32(p2peg, 0x224); reg32 &= ~(1 << 8); @@ -614,11 +608,9 @@ reg32 |= 1; pci_write_config32(p2peg, PEGSTS, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Force PCIRST# */ + pci_s_assert_secondary_reset(p2peg); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "PCIe link training ..."); timeout = 0x7ffff; @@ -774,17 +766,14 @@
MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 |= PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + /* Toggle PCIRST# */ + pci_s_assert_secondary_reset(p2peg);
reg32 = pci_read_config32(p2peg, 0x224); reg32 |= (1 << 8); pci_write_config32(p2peg, 0x224, reg32);
- reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL); - reg16 &= ~PCI_BRIDGE_CTL_BUS_RESET; - pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16); + pci_s_deassert_secondary_reset(p2peg);
printk(BIOS_DEBUG, "Wait for link to enter detect state... "); timeout = 0x7fffff; @@ -880,6 +869,14 @@ pci_write_config32(PCI_DEV(0, 0x1c, 0), 0xd8, 0x00110000); }
+void ich7_p2p_secondary_reset(void) +{ + pci_devfn_t p2p_bridge = PCI_DEV(0, 0x1e, 0); + pci_s_assert_secondary_reset(p2p_bridge); + mdelay(200); + pci_s_deassert_secondary_reset(p2p_bridge); +} + void i945_early_initialization(void) { /* Print some chipset specific information */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index d615b40..fec8919 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -39,6 +39,8 @@ void i82801gx_enable(struct device *dev); #endif
+void ich7_p2p_secondary_reset(void); + void enable_smbus(void);
#if ENV_ROMSTAGE