[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add FSP UPD for minimum assertion width

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30719

Change subject: soc/intel/cannonlake: Add FSP UPD for minimum assertion width
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soc/intel/cannonlake: Add FSP UPD for minimum assertion width

Expose the FSP tunables for the chipset minimum assertion width
settings which can be configured per-board.

The defaults appear to be different from what is listed in the FSP
header documentation so I tried to list what the actual default is
based on the source rather than what is stated the header comments.

Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca
Signed-off-by: Duncan Laurie 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
2 files changed, 47 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30719/1

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 3a723d2..6517b9e 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -222,6 +222,43 @@
     */
    uint32_t PrmrrSize;
    uint8_t PmTimerDisabled;
+
+	/*
+	 * SLP_S3 Minimum Assertion Width Policy
+	 *  1 = 60us
+	 *  2 = 1ms (default)
+	 *  3 = 50ms
+	 *  4 = 2s
+	 */
+	uint8_t PchPmSlpS3MinAssert;
+
+	/*
+	 * SLP_S4 Minimum Assertion Width Policy
+	 *  1 = 1s
+	 *  2 = 2s
+	 *  3 = 3s
+	 *  4 = 4s (default)
+	 */
+	uint8_t PchPmSlpS4MinAssert;
+
+	/*
+	 * SLP_SUS Minimum Assertion Width Policy
+	 *  1 = 0ms
+	 *  2 = 500ms
+	 *  3 = 1s (default)
+	 *  4 = 4s
+	 */
+	uint8_t PchPmSlpSusMinAssert;
+
+	/*
+	 * SLP_A Minimum Assertion Width Policy
+	 *  1 = 0ms
+	 *  2 = 4s
+	 *  3 = 98ms (default)
+	 *  4 = 2s
+	 */
+	uint8_t PchPmSlpAMinAssert;
+
    /* Desired platform debug type. */
    enum {
    	DebugConsent_Disabled,
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 8166dea..ea781bc 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -229,6 +229,16 @@
    /* Power Optimizer */
    params->PchPwrOptEnable = config->dmipwroptimize;
    params->SataPwrOptEnable = config->satapwroptimize;
+
+	/* Apply minimum assertion width settings if non-zero */
+	if (config->PchPmSlpS3MinAssert)
+		params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;
+	if (config->PchPmSlpS4MinAssert)
+		params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert;
+	if (config->PchPmSlpSusMinAssert)
+		params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert;
+	if (config->PchPmSlpAMinAssert)
+		params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert;
 }

/* Mainboard GPIO Configuration */