[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: add common function to set LT_LOCK_MEMORY

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36339 )

Change subject: soc/intel/common: add common function to set LT_LOCK_MEMORY
......................................................................

soc/intel/common: add common function to set LT_LOCK_MEMORY

Add a common function for setting LT_LOCK_MEMORY via MSR 0x2E7, which
locks most of the chipset BAR registers in accordance to Intel BWG.

Change-Id: I4ca719a9c81dca40181816d75f4dcadab257c0b3
Signed-off-by: Michael Niewöhner 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36339
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
---
M src/soc/intel/common/block/cpu/cpulib.c
M src/soc/intel/common/block/include/intelblocks/cpulib.h
M src/soc/intel/common/block/include/intelblocks/msr.h
3 files changed, 11 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved

diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c
index 75e7112..71e4dbf 100644
--- a/src/soc/intel/common/block/cpu/cpulib.c
+++ b/src/soc/intel/common/block/cpu/cpulib.c
@@ -23,10 +23,10 @@
 #include <arch/cpu.h>
 #include <intelblocks/cpulib.h>
 #include <intelblocks/fast_spi.h>
+#include <intelblocks/msr.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
 #include <soc/pm.h>
-#include <intelblocks/msr.h>
 #include <soc/pci_devs.h>
 #include <stdint.h>

@@ -320,3 +320,8 @@
    		(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
    }
 }
+
+void cpu_lt_lock_memory(void *unused)
+{
+	msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT);
+}
diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h
index 8630fd1..1aa88e1 100644
--- a/src/soc/intel/common/block/include/intelblocks/cpulib.h
+++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h
@@ -161,4 +161,7 @@
 /* Configure Machine Check Architecture support */
 void mca_configure(void);

+/* Lock chipset memory registers to protect SMM */
+void cpu_lt_lock_memory(void *unused);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_CPULIB_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 6fdf26e..3e67fd7 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -67,6 +67,8 @@
 #define MSR_POWER_CTL			0x1fc
 #define  POWER_CTL_C1E_MASK		(1 << 1)
 #define MSR_EVICT_CTL			0x2e0
+#define MSR_LT_CONTROL			0x2e7
+#define  LT_CONTROL_LOCK_BIT		(0)
 #define MSR_SGX_OWNEREPOCH0		0x300
 #define MSR_SGX_OWNEREPOCH1		0x301
 #define SMM_FEATURE_CONTROL_MSR		0x4e0