[coreboot-gerrit] Change in coreboot[master]: [WIP] chromeos.fmd for nissa

[Reka Norman (Code Review)]

Reka Norman has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59027 )

Change subject: [WIP] chromeos.fmd for nissa
......................................................................

[WIP] chromeos.fmd for nissa

This is my current estimate of the sizes required for each region on
nissa.

Change-Id: I3024f08a646f026c7d3d6652bcce645cd4932920
Signed-off-by: Reka Norman 
---
M src/mainboard/google/brya/chromeos.fmd
1 file changed, 14 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/59027/1

diff --git a/src/mainboard/google/brya/chromeos.fmd b/src/mainboard/google/brya/chromeos.fmd
index 72c6429..d2706d4 100644
--- a/src/mainboard/google/brya/chromeos.fmd
+++ b/src/mainboard/google/brya/chromeos.fmd
@@ -1,4 +1,4 @@
-FLASH 32M {
+FLASH 22044K {
    SI_ALL 5M {
    	SI_DESC 4K
    	SI_ME {
@@ -9,50 +9,40 @@
    		CSE_RW 3008K
    	}
    }
-	SI_BIOS 27M {
-		RW_SECTION_A 8M {
-			VBLOCK_A 64K
+	SI_BIOS 16924K {
+		RW_SECTION_A 5826K {
+			VBLOCK_A 8K
    		FW_MAIN_A(CBFS)
    		RW_FWID_A 64
    		ME_RW_A(CBFS) 3008K
    	}
-		RW_LEGACY(CBFS) 2M
-		RW_MISC 1M {
+		RW_LEGACY(CBFS) 1M
+		RW_MISC 152K {
    		UNIFIED_MRC_CACHE(PRESERVE) 128K {
    			RECOVERY_MRC_CACHE 64K
    			RW_MRC_CACHE 64K
    		}
-			RW_ELOG(PRESERVE) 16K
-			RW_SHARED 16K {
-				SHARED_DATA 8K
-				VBLOCK_DEV 8K
+			RW_ELOG(PRESERVE) 4K
+			RW_SHARED 4K {
+				SHARED_DATA 4K
    		}
-			# The RW_SPD_CACHE region is only used for brya variants that use DDRx memory.
-			# It is placed in the common `chromeos.fmd` file because it is only 4K and there
-			# is free space in the RW_MISC region that cannot be easily reclaimed because
-			# the RW_SECTION_B must start on the 16M boundary.
-			RW_SPD_CACHE(PRESERVE) 4K
    		RW_VPD(PRESERVE) 8K
-			RW_NVRAM(PRESERVE) 24K
+			RW_NVRAM(PRESERVE) 8K
    	}
-		# This section starts at the 16M boundary in SPI flash.
-		# ADL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 8M {
-			VBLOCK_B 64K
+		RW_SECTION_B 5826K {
+			VBLOCK_B 8K
    		FW_MAIN_B(CBFS)
    		RW_FWID_B 64
    		ME_RW_B(CBFS) 3008K
    	}
    	# Make WP_RO region align with SPI vendor
    	# memory protected range specification.
-		WP_RO 8M {
+		WP_RO 4M {
    		RO_VPD(PRESERVE) 16K
    		RO_SECTION {
    			FMAP 2K
    			RO_FRID 64
-				GBB@4K 448K
+				GBB@4K 12K
    			COREBOOT(CBFS)
    		}
    	}