Philipp M has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74173 )
Change subject: src/arch/ Fixed some linter warnings and errors ......................................................................
src/arch/ Fixed some linter warnings and errors
This is my first commit to coreboot, so please tell me if I'm missing something. I corrected some linter issues, deleting whitespaces, correcting identations etc. Some changes seemed like no big addition to readability to me, but I guess having everything more uniform is good.
Signed-off-by: Philipp Macher philipp-macher@web.de Change-Id: I976cffe971695f591ec42fce46e6743444277759 --- M src/arch/arm/include/arch/hlt.h M src/arch/arm/include/armv7/arch/cache.h M src/arch/arm64/include/arch/hlt.h M src/arch/riscv/include/mcall.h M src/arch/riscv/trap_handler.c M src/console/vtxprintf.c 6 files changed, 68 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/74173/1
diff --git a/src/arch/arm/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h index 7229643..7bdae39 100644 --- a/src/arch/arm/include/arch/hlt.h +++ b/src/arch/arm/include/arch/hlt.h @@ -5,7 +5,8 @@
static __always_inline void hlt(void) { - for (;;) ; + for (;;) + ; }
#endif /* ARCH_HLT_H */ diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index f10b8a0..1507df7 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -234,7 +234,7 @@ * Note: L2CTLR can only be written when the L2 memory system * is idle, ie before the MMU is enabled. */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" ); + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); isb(); }
@@ -249,7 +249,7 @@ /* write L2 Auxiliary Control Register (L2ACTLR) */ static inline void write_l2actlr(uint32_t val) { - asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" ); + asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory"); isb(); }
diff --git a/src/arch/arm64/include/arch/hlt.h b/src/arch/arm64/include/arch/hlt.h index 7229643..7bdae39 100644 --- a/src/arch/arm64/include/arch/hlt.h +++ b/src/arch/arm64/include/arch/hlt.h @@ -5,7 +5,8 @@
static __always_inline void hlt(void) { - for (;;) ; + for (;;) + ; }
#endif /* ARCH_HLT_H */ diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 803ee3e..7e56eac 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -57,11 +57,11 @@ #define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + (void *)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
// hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) +#define HLS() ((hls_t *)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t *)((void *)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id)))
#define MACHINE_STACK_SIZE RISCV_PGSIZE
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f5953d3..7d6e394 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -33,10 +33,10 @@ static const char *mstatus_to_previous_mode(uintptr_t ms) { switch (ms & MSTATUS_MPP) { - case 0x00000000: return "user"; - case 0x00000800: return "supervisor"; - case 0x00001000: return "hypervisor"; - case 0x00001800: return "machine"; + case 0x00000000: return "user"; + case 0x00000800: return "supervisor"; + case 0x00001000: return "hypervisor"; + case 0x00001800: return "machine"; }
return "unknown"; @@ -61,7 +61,7 @@ previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); printk(BIOS_DEBUG, "Hart ID: %d\n", hart_id); printk(BIOS_DEBUG, "Previous mode: %s%s\n", - previous_mode, mprv? " (MPRV)":""); + previous_mode, mprv ? " (MPRV)":""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]); @@ -117,31 +117,31 @@ }
switch (tf->cause) { - case CAUSE_MISALIGNED_FETCH: - case CAUSE_FETCH_ACCESS: - case CAUSE_ILLEGAL_INSTRUCTION: - case CAUSE_BREAKPOINT: - case CAUSE_LOAD_ACCESS: - case CAUSE_STORE_ACCESS: - case CAUSE_USER_ECALL: - case CAUSE_HYPERVISOR_ECALL: - case CAUSE_MACHINE_ECALL: - print_trap_information(tf); - break; - case CAUSE_SUPERVISOR_ECALL: - handle_sbi(tf); - return; - case CAUSE_MISALIGNED_LOAD: - case CAUSE_MISALIGNED_STORE: - print_trap_information(tf); - handle_misaligned(tf); - return; - default: - printk(BIOS_EMERG, "================================\n"); - printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); - printk(BIOS_EMERG, "================================\n"); - print_trap_information(tf); - break; + case CAUSE_MISALIGNED_FETCH: + case CAUSE_FETCH_ACCESS: + case CAUSE_ILLEGAL_INSTRUCTION: + case CAUSE_BREAKPOINT: + case CAUSE_LOAD_ACCESS: + case CAUSE_STORE_ACCESS: + case CAUSE_USER_ECALL: + case CAUSE_HYPERVISOR_ECALL: + case CAUSE_MACHINE_ECALL: + print_trap_information(tf); + break; + case CAUSE_SUPERVISOR_ECALL: + handle_sbi(tf); + return; + case CAUSE_MISALIGNED_LOAD: + case CAUSE_MISALIGNED_STORE: + print_trap_information(tf); + handle_misaligned(tf); + return; + default: + printk(BIOS_EMERG, "================================\n"); + printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "================================\n"); + print_trap_information(tf); + break; }
die("Can't recover from trap. Halting.\n"); diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index cfba6db..0de657e 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -127,11 +127,21 @@ repeat: ++fmt; /* this also skips first '%' */ switch (*fmt) { - case '-': flags |= LEFT; goto repeat; - case '+': flags |= PLUS; goto repeat; - case ' ': flags |= SPACE; goto repeat; - case '#': flags |= SPECIAL; goto repeat; - case '0': flags |= ZEROPAD; goto repeat; + case '-': + flags |= LEFT; + goto repeat; + case '+': + flags |= PLUS; + goto repeat; + case ' ': + flags |= SPACE; + goto repeat; + case '#': + flags |= SPECIAL; + goto repeat; + case '0': + flags |= ZEROPAD; + goto repeat; }
/* get field width */