Hello Patrick Rudolph, Angel Pons, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33565
to look at the new patch set (#4).
Change subject: mb/asrock/h110m: rewrite gpio config using macros ......................................................................
mb/asrock/h110m: rewrite gpio config using macros
This format of PCH GPIOs configuration, unlike the raw DW0/1 registers values from the inteltool log, is more understandable and makes the code much cleaner. However, macros from gpio_defs.h(1) can't determine the setting for each pads. The patch changes the format of the GPIO ports configuration for this motherboard using additional macros:
PAD_CFG_NF_TRIG_OFF(pad, pull, rst, func) PAD_CFG_NF_GPIO_DRIVER_HI_Z(pad, pull, rst, func) PAD_CFG_NF_GPIO_DRIVER_0(pad, pull, rst, func)
The pch-pads-parser(1) utility was used to create this configuration from inteltool logs. Now INTSEL field of the DW1 register(2) isn`t overwritten, since it is read-only.
[1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] https://github.com/maxpoliak/pch-pads-parser [3] p1431, Intel 100/C230 Series Chipset Family PCH Volume 2 (February 2019)
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/asrock/h110m/include/gpio.h 1 file changed, 247 insertions(+), 238 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33565/4