Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79792?usp=email )
Change subject: mb/google/skyrim: Update DXIO descriptor definition ......................................................................
mb/google/skyrim: Update DXIO descriptor definition
Update definition to be more intuitive and extensible. Port descriptors will be defined as individual entities and added to the descriptor list as such.
BUG=b:281059446 TEST=builds
Change-Id: I6a61d6561304782de847f6b99c9a73292e12b33f Signed-off-by: Jon Murphy jpmurphy@google.com --- M src/mainboard/google/guybrush/port_descriptors.c M src/mainboard/google/guybrush/variants/baseboard/Makefile.inc A src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c 5 files changed, 143 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/79792/1
diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index fc6ccb8..ea59103 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -7,93 +7,6 @@ #include <soc/platform_descriptors.h> #include <types.h>
-/* All PCIe Resets are handled in coreboot */ -static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { - { /* WLAN */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 0, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(WLAN_DEVFN), - .function_number = PCI_FUNC(WLAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = false, - .link_aspm_L1_2 = false, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* SD */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 1, - .end_logical_lane = 1, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(SD_DEVFN), - .function_number = PCI_FUNC(SD_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1, - .gpio_group_id = GPIO_69, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* WWAN */ - .engine_type = UNUSED_ENGINE, - .port_present = true, - .start_logical_lane = 2, - .end_logical_lane = 2, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(WWAN_DEVFN), - .function_number = PCI_FUNC(WWAN_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* NVME */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 4, - .end_logical_lane = 7, - .link_speed_capability = GEN3, - .device_number = PCI_SLOT(NVME_DEVFN), - .function_number = PCI_FUNC(NVME_DEVFN), - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* Dummy Device */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 11, - .device_number = PCIE_GPP_BRIDGE_2_DEV, - .function_number = PCIE_GPP_2_4_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - }, - { /* Dummy Device */ - .engine_type = PCIE_ENGINE, - .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 23, - .device_number = PCIE_GPP_BRIDGE_1_DEV, - .function_number = PCIE_GPP_1_0_FUNC, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6, - .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} - } -}; - static fsp_ddi_descriptor guybrush_czn_ddi_descriptors[] = { { /* DDI0 - eDP */ .connector_type = DDI_EDP, @@ -122,10 +35,6 @@ } };
-void __weak variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors) -{ -} - void __weak variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors) { } @@ -134,23 +43,9 @@ const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) { - /* Get Variant specific SD AUX Reset GPIO */ - guybrush_czn_dxio_descriptors[SD].gpio_group_id = variant_sd_aux_reset_gpio(); - - /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it - is enabled. */ - if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) - guybrush_czn_dxio_descriptors[WWAN_NVME].engine_type = PCIE_ENGINE; - - if (variant_has_pcie_wwan()) - guybrush_czn_dxio_descriptors[WWAN_NVME].gpio_group_id = GPIO_18; - - variant_update_dxio_descriptors(guybrush_czn_dxio_descriptors); + variant_get_dxio_descriptors(dxio_descs, dxio_num); variant_update_ddi_descriptors(guybrush_czn_ddi_descriptors);
- *dxio_descs = guybrush_czn_dxio_descriptors; - *dxio_num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); - *ddi_descs = guybrush_czn_ddi_descriptors; *ddi_num = ARRAY_SIZE(guybrush_czn_ddi_descriptors); } diff --git a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc index 74d030d..014dfd6 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/baseboard/Makefile.inc @@ -3,11 +3,13 @@ bootblock-y += gpio.c bootblock-y += helpers.c
-romstage-y += helpers.c romstage-y += gpio.c +romstage-y += helpers.c +romstage-y += port_descriptors.c
ramstage-y += gpio.c ramstage-y += helpers.c +ramstage-y += port_descriptors.c
verstage-y += gpio.c
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h new file mode 100644 index 0000000..528e2a9 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/port_descriptors.h @@ -0,0 +1,93 @@ +#ifndef __BASEBOARD_PORT_DESCRIPTORS_H__ +#define __BASEBOARD_PORT_DESCRIPTORS_H__ + +#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN +#define SD_DEVFN PCIE_GPP_2_1_DEVFN +#define WWAN_DEVFN PCIE_GPP_2_2_DEVFN +#define NVME_DEVFN PCIE_GPP_2_3_DEVFN + +#define WLAN_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 0, \ + .end_logical_lane = 0, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(WLAN_DEVFN), \ + .function_number = PCI_FUNC(WLAN_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = false, \ + .link_aspm_L1_2 = false, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ0, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define SD_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 1, \ + .end_logical_lane = 1, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(SD_DEVFN), \ + .function_number = PCI_FUNC(SD_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ1, \ + .gpio_group_id = GPIO_69, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define WWAN_DXIO_DESCRIPTOR { \ + .engine_type = UNUSED_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 2, \ + .end_logical_lane = 2, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(WWAN_DEVFN), \ + .function_number = PCI_FUNC(WWAN_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ2, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define NVME_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 4, \ + .end_logical_lane = 7, \ + .link_speed_capability = GEN3, \ + .device_number = PCI_SLOT(NVME_DEVFN), \ + .function_number = PCI_FUNC(NVME_DEVFN), \ + .link_aspm = ASPM_L1, \ + .link_aspm_L1_1 = true, \ + .link_aspm_L1_2 = true, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ3, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define DUMMY_1_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 8, \ + .end_logical_lane = 11, \ + .device_number = PCIE_GPP_BRIDGE_2_DEV, \ + .function_number = PCIE_GPP_2_4_FUNC, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ5, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} +#define DUMMY_2_DXIO_DESCRIPTOR { \ + .engine_type = PCIE_ENGINE, \ + .port_present = true, \ + .start_logical_lane = 16, \ + .end_logical_lane = 23, \ + .device_number = PCIE_GPP_BRIDGE_1_DEV, \ + .function_number = PCIE_GPP_1_0_FUNC, \ + .turn_off_unused_lanes = true, \ + .clk_req = CLK_REQ6, \ + .port_params = {PP_PSPP_AC, 0x133, PP_PSPP_DC, 0x122} \ +} + +#endif //__BASEBOARD_PORT_DESCRIPTORS_H__ diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h index 9f99b9f..9b39003 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h @@ -7,11 +7,6 @@ #include <soc/pci_devs.h> #include <platform_descriptors.h>
-#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN -#define SD_DEVFN PCIE_GPP_2_1_DEVFN -#define WWAN_DEVFN PCIE_GPP_2_2_DEVFN -#define NVME_DEVFN PCIE_GPP_2_3_DEVFN - /* This function provides base GPIO configuration table. */ const struct soc_amd_gpio *baseboard_gpio_table(size_t *size); /* @@ -40,15 +35,13 @@
bool variant_has_pcie_wwan(void);
-void variant_update_dxio_descriptors(fsp_dxio_descriptor *dxio_descriptors); void variant_update_ddi_descriptors(fsp_ddi_descriptor *ddi_descriptors);
-enum dxio_port_id { - WLAN, - SD, - WWAN_NVME, - NVME -}; +/* + * This function allows a variant to override dxio descriptors passed to the FSP. + */ +void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, + size_t *num);
uint8_t variant_sd_aux_reset_gpio(void);
diff --git a/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c new file mode 100644 index 0000000..b2bea12 --- /dev/null +++ b/src/mainboard/google/guybrush/variants/baseboard/port_descriptors.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <baseboard/port_descriptors.h> +#include <device/device.h> +#include <soc/platform_descriptors.h> + +enum baseboard_dxio_port_id { + BASEBOARD_DXIO_WLAN, + BASEBOARD_DXIO_SD, + BASEBOARD_DXIO_WWAN_NVME, + BASEBOARD_DXIO_NVME, + BASEBOARD_DXIO_DUMMY_1, + BASEBOARD_DXIO_DUMMY_2, +}; + +static fsp_dxio_descriptor guybrush_czn_dxio_descriptors[] = { + [BASEBOARD_DXIO_WLAN] = WLAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_SD] = SD_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_WWAN_NVME] = WWAN_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_NVME] = NVME_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_DUMMY_1] = DUMMY_1_DXIO_DESCRIPTOR, + [BASEBOARD_DXIO_DUMMY_2] = DUMMY_2_DXIO_DESCRIPTOR, +}; + +__weak void variant_get_dxio_descriptors(const fsp_dxio_descriptor **dxio_descriptor, size_t *num) +{ + /* Get Variant specific SD AUX Reset GPIO */ + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_SD].gpio_group_id = variant_sd_aux_reset_gpio(); + + /* gpp_bridge_2 is used either for WWAN or NVME bridge. Mark it as PCIE_ENGINE when it + is enabled. */ + if (is_dev_enabled(DEV_PTR(gpp_bridge_2))) + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_WWAN_NVME].engine_type = PCIE_ENGINE; + + if (variant_has_pcie_wwan()) + guybrush_czn_dxio_descriptors[BASEBOARD_DXIO_WWAN_NVME].gpio_group_id = GPIO_18; + + *dxio_descriptor = guybrush_czn_dxio_descriptors; + *num = ARRAY_SIZE(guybrush_czn_dxio_descriptors); +}