[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Add memory configuration support for Jasper Lake

[Meera Ravindranath (Code Review)]

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39135 )

Change subject: src/soc/tigerlake: Add memory configuration support for Jasper Lake
......................................................................

Patch Set 13:

(3 comments)

https://review.coreboot.org/c/coreboot/+/39135/12/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit_jsl.h:

https://review.coreboot.org/c/coreboot/+/39135/12/src/soc/intel/tigerlake/in... 
PS12, Line 4: Copyright (C) Intel Corporation 2020.
> Copyright (C) 2020 Intel Corporation.

Done

https://review.coreboot.org/c/coreboot/+/39135/11/src/soc/intel/tigerlake/in... 
File src/soc/intel/tigerlake/include/soc/meminit_jsl.h:

https://review.coreboot.org/c/coreboot/+/39135/11/src/soc/intel/tigerlake/in... 
PS11, Line 4:  * Copyright Intel Corporation 2020.
> please use header as you did here […]

Done

https://review.coreboot.org/c/coreboot/+/39135/11/src/soc/intel/tigerlake/me... 
File src/soc/intel/tigerlake/meminit_jsl.c:

https://review.coreboot.org/c/coreboot/+/39135/11/src/soc/intel/tigerlake/me... 
PS11, Line 4:  * Copyright Intel Corporation 2020.
> same here https://review.coreboot.org/c/coreboot/+/39136/9/src/mainboard/google/dedede.... […]

Done