Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30561
Change subject: soc/intel/cannonlake: Add support to enable/disable USB charging in s3/S5 ......................................................................
soc/intel/cannonlake: Add support to enable/disable USB charging in s3/S5
BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: I555bb8d763bbc0b693536e34e0a5bf9375e3259a Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/cannonlake/acpi/globalnvs.asl 1 file changed, 27 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30561/1
diff --git a/src/soc/intel/cannonlake/acpi/globalnvs.asl b/src/soc/intel/cannonlake/acpi/globalnvs.asl index ac60b36..1bd3038 100644 --- a/src/soc/intel/cannonlake/acpi/globalnvs.asl +++ b/src/soc/intel/cannonlake/acpi/globalnvs.asl @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -50,8 +50,34 @@ U2WE, 16, // 0x2b - 0x2c USB2 Wake Enable Bitmap U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume + S5U0, 8, // 0x30 - Enable USB in S5 + S3U0, 8, // 0x31 - Enable USB in S3
/* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> } + +/* Set flag to enable USB charging in S3 */ +Method (S3UE) +{ + Store (One, \S3U0) +} + +/* Set flag to disable USB charging in S3 */ +Method (S3UD) +{ + Store (Zero, \S3U0) +} + +/* Set flag to enable USB charging in S5 */ +Method (S5UE) +{ + Store (One, \S5U0) +} + +/* Set flag to disable USB charging in S5 */ +Method (S5UD) +{ + Store (Zero, \S5U0) +}