Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39601 )
Change subject: soc/intel/xeon_sp: Refactor code to allow for additional CPUs types
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Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39601/6/src/soc/intel/xeon_sp/util....
File src/soc/intel/xeon_sp/util.c:
https://review.coreboot.org/c/coreboot/+/39601/6/src/soc/intel/xeon_sp/util....
PS6, Line 60: uint32_t bus = pci_io_read_config32(PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV,
Is there a reason to use PCI IO cfg (0xcf8/0xcfc) here? Same question for function above.
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