[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Support ISH

[Li1 Feng (Code Review)]

Hello build bot (Jenkins), Wonkyu Kim, Raj Astekar, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39480

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Support ISH
......................................................................

soc/intel/tigerlake: Support ISH

Add ACPI Object for ISH SSDT
Enable/disable ISH based on devicetree

BRANCH=none
BUG=b:145946347
TEST=build successfully and boot to OS with TGLRVP UP3

Signed-off-by: Hu, Hebo 
Signed-off-by: li feng 
Change-Id: I30f4d936ece139cf67640e6df6a9f47579f87bca
---
A src/soc/intel/tigerlake/acpi/ish.asl
M src/soc/intel/tigerlake/acpi/southbridge.asl
M src/soc/intel/tigerlake/chip.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
4 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39480/6