[coreboot-gerrit] Change in ...coreboot[master]: riscv: use mret to invoke M-mode payload and disable interrupts

[Xiang Wang (Code Review)]

Hello Patrick Rudolph, Patrick Rudolph, build bot (Jenkins), Philipp Hug,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/33462

to look at the new patch set (#3).

Change subject: riscv: use mret to invoke M-mode payload and disable interrupts
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riscv: use mret to invoke M-mode payload and disable interrupts

Fixes a logic error that sets MPIE, but didn't use mret to return to the payload.
This left MIE set to an undefined value.

Now all modes are handled the same way:
- Trap vector base address point to the payload
- Disable Interrupt
- Return to payload using mret

TEST=Run an M-mode payload

Change-Id: Iaab595f916949c57104ec00f8b06ea047fe76bba
Signed-off-by: Xiang Wang 
---
M src/arch/riscv/payload.c
1 file changed, 20 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/33462/3