[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
PS9, Line 167: 	/* Cache the ROM as WP just below 4GiB. */
> > You ** NEED ** to make the perfomance comparison with TSEG marked WB.
>
> can you please submit that CL to enable TSEG range marked WB and share the savings because its your idea.

No hardware to test here. Just copy the three lines from somewhere. As far as I am concerned that is a bug in original cannonlake work that was submitted. No clue why it was removed. And why some platforms guarded it with CONFIG(HAVE_SMI_HANDLER).