[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power ...

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jamie Chen, Tim Wawrzynczak.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63675 )

Change subject: soc/intel/jasperlake: CNVi: Enable fewer wakeups to reduce SoC power consumption
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Patch Set 5:

(3 comments)

Patchset:

PS5: 
Sorry for chiming in late.

File src/soc/intel/jasperlake/chip.h:

https://review.coreboot.org/c/coreboot/+/63675/comment/66230eb9_87e5dca2 
PS5, Line 428:  * Setting this on a system that supports S0i3 (set xtalsdqdis [Bit 22] in
             : 	 * cppmvric1 register to 0) will break CNVI timing.
Should we have to assert xtalsdqdis bit is not set when this bit is set?

File src/soc/intel/jasperlake/finalize.c:

https://review.coreboot.org/c/coreboot/+/63675/comment/8258b873_63e50c57 
PS5, Line 63: 		if (config->cnvi_reduce_s0ix_pwr_usage) {
Also should we have to ensure that CNVI device is enabled in the devicetree. What is the impact of setting this on boards that use discrete WiFi?