[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common/acpi: Add common CPU methods

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29754

Change subject: soc/intel/common/acpi: Add common CPU methods
......................................................................

soc/intel/common/acpi: Add common CPU methods

Add a common ASL file for expected CPU methods so it does not need
to be duplicated in every SOC implementation.

Change-Id: Ifd467ef84a391698cd395172c3f0d4e801bdd09b
Signed-off-by: Duncan Laurie 
---
A src/soc/intel/common/acpi/cpu.asl
1 file changed, 118 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29754/1

diff --git a/src/soc/intel/common/acpi/cpu.asl b/src/soc/intel/common/acpi/cpu.asl
new file mode 100644
index 0000000..79eaac4
--- /dev/null
+++ b/src/soc/intel/common/acpi/cpu.asl
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* These devices are created at runtime */
+External (_PR.CP00, DeviceObj)
+External (_PR.CP01, DeviceObj)
+External (_PR.CP02, DeviceObj)
+External (_PR.CP03, DeviceObj)
+External (_PR.CP04, DeviceObj)
+External (_PR.CP05, DeviceObj)
+External (_PR.CP06, DeviceObj)
+External (_PR.CP07, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (_PR.CP00, 0x81)  // _CST
+		Notify (_PR.CP01, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (_PR.CP02, 0x81)  // _CST
+		Notify (_PR.CP03, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (_PR.CP04, 0x81)  // _CST
+		Notify (_PR.CP05, 0x81)  // _CST
+		Notify (_PR.CP06, 0x81)  // _CST
+		Notify (_PR.CP07, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (_PR.CP00, 0x80)  // _PPC
+		Notify (_PR.CP01, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (_PR.CP02, 0x80)  // _PPC
+		Notify (_PR.CP03, 0x80)  // _PPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (_PR.CP04, 0x80)  // _PPC
+		Notify (_PR.CP05, 0x80)  // _PPC
+		Notify (_PR.CP06, 0x80)  // _PPC
+		Notify (_PR.CP07, 0x80)  // _PPC
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (_PR.CP00, 0x82)  // _TPC
+		Notify (_PR.CP01, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (_PR.CP02, 0x82)  // _TPC
+		Notify (_PR.CP03, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (_PR.CP04, 0x82)  // _TPC
+		Notify (_PR.CP05, 0x82)  // _TPC
+		Notify (_PR.CP06, 0x82)  // _TPC
+		Notify (_PR.CP07, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 8)) {
+		Return (Package()
+		{
+			_PR.CP00,
+			_PR.CP01,
+			_PR.CP02,
+			_PR.CP03,
+			_PR.CP04,
+			_PR.CP05,
+			_PR.CP06,
+			_PR.CP07
+		})
+	} ElseIf (LGreaterEqual (\PCNT, 4)) {
+		Return (Package ()
+		{
+			_PR.CP00,
+			_PR.CP01,
+			_PR.CP02,
+			_PR.CP03
+		})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package ()
+		{
+			_PR.CP00,
+			_PR.CP01
+		})
+	} Else {
+		Return (Package ()
+		{
+			_PR.CP00
+		})
+	}
+}