[coreboot-gerrit] Change in coreboot[master]: cpu/intel/common: Extend FSB detection to cover TSC

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31340 )

Change subject: cpu/intel/common: Extend FSB detection to cover TSC
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Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31340/11/src/cpu/intel/common/fsb.c 
File src/cpu/intel/common/fsb.c:

https://review.coreboot.org/c/coreboot/+/31340/11/src/cpu/intel/common/fsb.c... 
PS11, Line 50: 			*ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24;
> This rdmsr resets my getac p470 (family 06, model 0f, stepping 06), despite the claim of table 2-48  […]

Hmm.. looking at CB:34200, which would remove i945/udelay.c, IA32_PERF_STATUS MSR 0x198 would have the ratio we want for tsc_freq_mhz() implementation?

Motivation for these changes is to have single udelay() for different stages, and have it run from monotonic timer.