[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/34791/13/src/soc/intel/cannonlake/r... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/13/src/soc/intel/cannonlake/r... 
PS13, Line 159: 	top_of_ram -= top_of_ram_size;
If cbmem_top() is 16 MiB aligned, it is very well hidden from the reader.