[coreboot-gerrit] Change in coreboot[master]: soc/intel/apl: enable lpc at bootblock

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31371 )

Change subject: soc/intel/apl: enable lpc at bootblock
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Patch Set 9:

(3 comments)

https://review.coreboot.org/c/coreboot/+/31371/7//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/31371/7//COMMIT_MSG@9 
PS7, Line 9: Serial console can be attached to lpc bus. Enable it for early debug
> Please add a dot/period at the end.

Done

https://review.coreboot.org/c/coreboot/+/31371/6/src/lib/bootblock.c 
File src/lib/bootblock.c:

https://review.coreboot.org/c/coreboot/+/31371/6/src/lib/bootblock.c@11 
PS6, Line 11: #include <reset.h>
> Why is this in here?

Bad push, fixed.

https://review.coreboot.org/c/coreboot/+/31371/7/src/soc/intel/apollolake/lp... 
File src/soc/intel/apollolake/lpc.c:

https://review.coreboot.org/c/coreboot/+/31371/7/src/soc/intel/apollolake/lp... 
PS7, Line 50: 0x00
> 0x0?

`0x00` is how I remind myself that we write bytes. I would understand `0`
but why `0x0`? It just looks like a weird emoticon.