Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42740 )
Change subject: mb/google/sarien: Enable bayhub 720 on Sarien ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/42740/4/src/mainboard/google/sarien... PS4, Line 388: device pci 1a.0 off end # eMMC : device pci 1c.0 on end # PCI Express Port 1 (USB) : device pci 1c.1 off end # PCI Express Port 2 (USB) : device pci 1c.2 off end # PCI Express Port 3 (USB) : device pci 1c.3 off end # PCI Express Port 4 (USB) : device pci 1c.4 off end # PCI Express Port 5 (USB) : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 on end # PCI Express Port 8 : device pci 1d.0 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "2230" "SlotDataBusWidth1X" : end # PCI Express Port 9 : device pci 1d.1 on end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 : device pci 1d.4 on : chip drivers/generic/bayhub : register "power_saving" = "1" : device pci 00.0 on end : end : smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" : end # PCI Express Port 13 (x4) : device pci 1e.0 off end # UART #0 : device pci 1e.1 off end # UART #1 : device pci 1e.2 off end # GSPI #0 : device pci 1e.3 off end # GSPI #1 : device pci 1f.0 on : chip ec/google/wilco : device pnp 0c09.0 on end : end This is also needed on Arcada as well as there is no shared devicetree.cb, correct?