Jingle Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35367 )
Change subject: mb/ocp/monolake: Add GPIO table and initialize ......................................................................
mb/ocp/monolake: Add GPIO table and initialize
Add GPIO table for Monolake to initialize GPIOs. Tested on Monolake
Change-Id: I74906bf9395a333be6250ffbd181da536e016f30 Signed-off-by: Jingle Hsu jingle_hsu@wiwynn.com --- A src/mainboard/ocp/monolake/gpio.h M src/mainboard/ocp/monolake/romstage.c 2 files changed, 106 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35367/1
diff --git a/src/mainboard/ocp/monolake/gpio.h b/src/mainboard/ocp/monolake/gpio.h new file mode 100644 index 0000000..982daa4 --- /dev/null +++ b/src/mainboard/ocp/monolake/gpio.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#ifndef MONOLAKE_GPIO_H +#define MONOLAKE_GPIO_H + +static const struct gpio_config gpio_tables[] = { + {0, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {1, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {2, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {3, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {4, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {5, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {6, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {7, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {8, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {9, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {10, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {11, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {12, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {13, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {14, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {15, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {16, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {17, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {18, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {19, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {20, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {21, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {22, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {23, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {24, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {25, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {26, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {27, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {28, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {29, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {30, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {31, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {32, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {33, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {34, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {35, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {36, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {37, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {38, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {39, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {40, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {41, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {42, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {43, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {44, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {45, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {46, GPIO_MODE_GPIO, GPIO_OUTPUT, GPIO_OUT_LEVEL_HIGH, 0, 0}, + {47, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {48, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {49, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {50, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {51, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {52, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {53, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {54, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {55, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {56, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {57, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {58, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {59, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {60, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {61, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {62, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {63, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {64, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {65, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {66, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {67, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {68, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {69, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {70, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {71, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {72, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {73, GPIO_MODE_GPIO, GPIO_INPUT, 0, 0, 0}, + {74, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {75, GPIO_MODE_NATIVE, 0, 0, 0, 0}, + {0xff, GPIO_LIST_END, 0, 0, 0, 0}, +}; + +#endif diff --git a/src/mainboard/ocp/monolake/romstage.c b/src/mainboard/ocp/monolake/romstage.c index 8625868..d7f2c3a 100644 --- a/src/mainboard/ocp/monolake/romstage.c +++ b/src/mainboard/ocp/monolake/romstage.c @@ -24,6 +24,8 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/lpc.h> +#include <soc/gpio.h> +#include "gpio.h"
/* Define the strings for UPD variables that could be customized */ #define FSP_VAR_HYPERTHREADING "HyperThreading" @@ -59,6 +61,9 @@ // IPMI through BIC pci_write_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_GEN2_DEC, 0x0c0ca1); + + // Initialize GPIOs + init_gpios(gpio_tables); }
/*