Werner Zeh (werner.zeh@siemens.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8399
-gerrit
commit 01a56f4ea0ff442252dbd211b5b9179e26b7e6bb Author: Werner Zeh werner.zeh@siemens.com Date: Tue Feb 10 10:16:12 2015 +0100
fsp_baytrail: Add new microcode for Bay Trail M
Add a new microcode for Bay Trail M D0 stepping used in cpu N2807 silicon. In addition, a selection of the used CPU type has been added (I or M/D) which allows to use only the really needed microcode for a given CPU type.
Change-Id: I373fc9b535f1dc97eaa9f76ae46f0b69b247a8a0 Signed-off-by: Werner Zeh werner.zeh@siemens.com --- src/soc/intel/fsp_baytrail/Kconfig | 9 +++++++++ src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 15 ++++++++++----- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 6 +++++- 3 files changed, 24 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 639071a..54ce836 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -51,6 +51,15 @@ config CPU_SPECIFIC_OPTIONS select CPU_MICROCODE_ADDED_DURING_BUILD if INCLUDE_MICROCODE_IN_BUILD select ROMSTAGE_RTC_INIT
+choice + prompt "Bay Trail CPU type" + default SOC_INTEL_FSP_BAYTRAIL_I +config SOC_INTEL_FSP_BAYTRAIL_I + bool "I" +config SOC_INTEL_FSP_BAYTRAIL_MD + bool "M/D" +endchoice + config BOOTBLOCK_CPU_INIT string default "soc/intel/fsp_baytrail/bootblock/bootblock.c" diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 709ff92..7ac1e7e 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,12 +19,17 @@
unsigned microcode[] = {
-/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ -#include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 -#include "M0130679901.h" // M0130679: Baytrail I D0 +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) + /* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ + #include "M0230672228.h" // M0230672: Bay Trail "Super SKU" B0/B1 + #include "M0130673322.h" // M0130673: Bay Trail I B2 / B3 + #include "M0130679901.h" // M0130679: Bay Trail I D0 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + /* Region size is 0x10000 - update in microcode_size.h if it gets larger. */ + #include "M0C30678829.h" // M0C30678: Bay Trail M D Stepping +#endif
- /* Dummy terminator */ + /* Dummy terminator */ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index ec55314..213fc17 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,6 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x30000 +#if IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_I) + #define MICROCODE_REGION_LENGTH 0x30000 +#elif IS_ENABLED(CONFIG_SOC_INTEL_FSP_BAYTRAIL_MD) + #define MICROCODE_REGION_LENGTH 0x10000 +#endif