[coreboot-gerrit] Change in coreboot[master]: asus/f2a85-m: move the rest of romstage.c code to bootblock.c

[Mike Banon (Code Review)]

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38272 )

Change subject: asus/f2a85-m: move the rest of romstage.c code to bootblock.c
......................................................................

asus/f2a85-m: move the rest of romstage.c code to bootblock.c

Move the rest of romstage.c code to bootblock.c. Based on a
similar change which worked fine for ASUS A88XM-E at CB:30987.

Signed-off-by: Mike Banon 
Change-Id: Ia2c686f845b6b403c65ac361487834c5b7671cf0
---
M src/mainboard/asus/f2a85-m/bootblock.c
D src/mainboard/asus/f2a85-m/romstage.c
2 files changed, 23 insertions(+), 47 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38272/1

diff --git a/src/mainboard/asus/f2a85-m/bootblock.c b/src/mainboard/asus/f2a85-m/bootblock.c
index 648f55a..b442732 100644
--- a/src/mainboard/asus/f2a85-m/bootblock.c
+++ b/src/mainboard/asus/f2a85-m/bootblock.c
@@ -14,29 +14,43 @@
  * GNU General Public License for more details.
  */

+#include <amdblocks/acpimmio.h>
 #include <bootblock_common.h>
 #include <device/pnp_type.h>
-#include <southbridge/amd/common/amd_defs.h>
-#include <stdint.h>
 #include <superio/ite/common/ite.h>
 #include <superio/ite/it8728f/it8728f.h>
 #include <superio/nuvoton/common/nuvoton.h>
 #include <superio/nuvoton/nct6779d/nct6779d.h>
+#include <southbridge/amd/agesa/hudson/smbus.h>

-#define SB_MMIO_MISC32(x) *(volatile u32 *)(AMD_SB_ACPI_MMIO_ADDR + 0xE00 + (x))
+static void smbus_setup(void)
+{
+	/* turn on secondary smbus at b20 */
+	u32 reg32;
+	reg32 = misc_read32(0x28);
+	reg32 |= 0x00000001;
+	misc_write32(0x28, reg32);
+
+	/* set DDR3 voltage */
+	reg32 = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
+
+	/* default is reg32 = 0x0, so no need to set it in this case */
+	if (reg32)
+		do_smbus_write_byte(0xb20, 0x15, 0x3, reg32);
+}

static void sbxxx_enable_48mhzout(void)
 {
    /* most likely programming to 48MHz out signal */
    u32 reg32;
-	reg32 = SB_MMIO_MISC32(0x28);
+	reg32 = misc_read32(0x28);
    reg32 &= 0xffc7ffff;
    reg32 |= 0x00100000;
-	SB_MMIO_MISC32(0x28) = reg32;
+	misc_write32(0x28, reg32);

-	reg32 = SB_MMIO_MISC32(0x40);
+	reg32 = misc_read32(0x40);
    reg32 &= ~0x80u;
-	SB_MMIO_MISC32(0x40) = reg32;
+	misc_write32(0x40, reg32);
 }

static void superio_init_m(void)
@@ -58,6 +72,8 @@

void bootblock_mainboard_early_init(void)
 {
+	smbus_setup();
+
    /* enable SIO clock */
    sbxxx_enable_48mhzout();

diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c
deleted file mode 100644
index 3aa29c8..0000000
--- a/src/mainboard/asus/f2a85-m/romstage.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- * Copyright (C) 2012 Rudolf Marek 
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <southbridge/amd/agesa/hudson/smbus.h>
-#include <stdint.h>
-
-void board_BeforeAgesa(struct sysinfo *cb)
-{
-	u8 byte;
-
-	post_code(0x30);
-
-	/* turn on secondary smbus at b20 */
-	outb(0x28, 0xcd6);
-	byte = inb(0xcd7);
-	byte |= 1;
-	outb(byte, 0xcd7);
-
-	/* set DDR3 voltage */
-	byte = CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_VAL;
-
-	/* default is byte = 0x0, so no need to set it in this case */
-	if (byte)
-		do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
-}