[coreboot-gerrit] Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded

[Angel Pons (Code Review)]

Attention is currently required from: Arthur Heymans, Patrick Georgi, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, Sridhar Siricilla, Werner Zeh, Angel Pons, Patrick Rudolph.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62566 )

Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62566/comment/945fa5d9_e7ed73a3 
PS2, Line 15: Now, in this scenario, the SPI
            : flash linear address range is not registered as a resource (since the
            : common SPI driver in src/soc/intel/common/block/spi is shared across
            : multiple SPI controllers and therefore cannot distinguish where the
            : flash is actually located at)
> Yes, like Angel mentioned already the fast_spi driver is not bound to a PCI device. […]

Actually, I'm not sure what would happen on systems without SPI flash. I think it's possible to have boot firmware in eMMC, and it would still be memory-mapped. Hmmm, if this can happen, we should declare the resource from the LPC/eSPI device instead.