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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56807
to look at the new patch set (#3).
Change subject: soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configuration ......................................................................
soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configuration
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO configuration register and drives it as output, so don't initially configure the GPIO as input with no pull up/down. This is a preparation to use the common AMD GPIO access functions instead of the raw register accesses, since the gpio_set function only sets the output value, but doesn't reconfigure the direction. Using gpio_output there instead would reconfigure the direction as well, but would result in doubling the number of MMIO accesses, so just configure the GPIOs correctly right away to avoid that.
TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks exactly the same as before during the reset_i2c_peripherals call. This was probed at the SCL pad of the unpopulated I2C level shifter on the side that is connected to the SoC.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5 --- M src/soc/amd/cezanne/early_fch.c M src/soc/amd/picasso/early_fch.c M src/soc/amd/stoneyridge/bootblock.c 3 files changed, 13 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/56807/3