[coreboot-gerrit] Change in coreboot[master]: mb/intel/shadowmountain: Add the ramstage code

[Angel Pons (Code Review)]

Attention is currently required from: V Sowmya, Martin Roth, Tim Wawrzynczak, Balaji Manigandan.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49732 )

Change subject: mb/intel/shadowmountain: Add the ramstage code
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Patch Set 6:

(3 comments)

File src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/49732/comment/f8954d12_7b3cbed8 
PS6, Line 91: 		[PchSerialIoIndexGSPI3] = 0,
Since GSPI2 and GSPI3 are disabled, I'd remove the settings for them here

https://review.coreboot.org/c/coreboot/+/49732/comment/0267108b_d5859ca5 
PS6, Line 98: 		[PchSerialIoIndexGSPI3] = 0,
Since GSPI2 and GSPI3 are disabled, I'd remove the settings for them here

https://review.coreboot.org/c/coreboot/+/49732/comment/492ada88_7353f3fc 
PS6, Line 148: cr50 TPM
Does shadowmountain have a cr50?