[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Subrata Banik (Code Review)]

Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, David Guckian, Vanny E, Kane Chen, Aamir Bohra, V Sowmya, build bot (Jenkins), David Guckian, Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/34995

to look at the new patch set (#12).

Change subject: arch/x86: Cache the TSEG region at the top of ram
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arch/x86: Cache the TSEG region at the top of ram

This patch adds new API for enabling caching for the TSEG region
and setting up required MTRR for next stage.

BUG=b:140008206
TEST=Build and boot CML-Hatch.

Change-Id: I59432c02e04af1b931d77de3f6652b0327ca82bb
Signed-off-by: Subrata Banik 
---
M src/arch/x86/include/arch/romstage.h
M src/arch/x86/postcar_loader.c
2 files changed, 27 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/34995/12