[coreboot-gerrit] Change in ...coreboot[master]: riscv: use mret to invoke M-mode payload and disable interrupts

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33462 )

Change subject: riscv: use mret to invoke M-mode payload and disable interrupts
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Patch Set 3:
> Patch Set 2:
> > Patch Set 2:
> > > Patch Set 2: Code-Review+1
> > >
> > > Thanks!
> > > Please change "riscv: fix run_payload" to something more specific.
> >
> > Do you have suggest?
> > > Also mention how the change has been tested.
> >
> > I read this code and found a logic error when setting the MPP field of mstatus.
> > If you do not return via mret, MPIE will not work.
> > I have only tested the situation of return to M-Mode.
>
> e.g.
>
> riscv: use mret to invoke M-mode payload and disable interrupts
>
> Fixes a logic error that sets MPIE, but didn't use mret to return to the payload. This left MIE set to an undefined value.
>
> Now all modes are handled the same way:
> Trap vector base address point to the payload
> Disable Interrupt
> Return to payload using mret
>
> TEST=Run an M-mode payload

Thank you very much!