Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44467 )
Change subject: mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO ......................................................................
mb/google/fizz/endeavour/gpio: Undo set DRIVER for GPO
GPIO Driver mode is used for configuration interrupt routing for external devices through GPI. But there is no point in configuring this for GPO. This patch replaces the PAD_CFG_GPO_GPIO_DRIVER macro with others that do not set the corresponding bit in the Host Software Pad Ownership register.
Change-Id: Icbbc644adda0dde768171e9581ae345cb9750eea Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/google/fizz/variants/endeavour/gpio.c 1 file changed, 4 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44467/1
diff --git a/src/mainboard/google/fizz/variants/endeavour/gpio.c b/src/mainboard/google/fizz/variants/endeavour/gpio.c index 432a180..716be3f 100644 --- a/src/mainboard/google/fizz/variants/endeavour/gpio.c +++ b/src/mainboard/google/fizz/variants/endeavour/gpio.c @@ -28,9 +28,9 @@ /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* ISH_GP0 */ PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A19, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* 7322_OE */ /* ISH_GP2 */ PAD_CFG_GPI_INT(GPP_A20, NONE, PLTRST, LEVEL), /* 7322_INTO */ -/* ISH_GP3 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_A21, 1, DEEP, NONE), /* 7322_OE */ +/* ISH_GP3 */ PAD_CFG_GPO(GPP_A21, 1, DEEP), /* 7322_OE */ /* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
@@ -134,13 +134,11 @@ /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* MB_PCIE_SATA#_DET */ /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E3, 0, DEEP, - NONE), /* TPU_RST_PIN40 */ +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 0, DEEP), /* TPU_RST_PIN40 */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* TP103 */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_MB */ /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* DEVSLP2_DB */ -/* CPU_GP1 */ PAD_CFG_GPO_GPIO_DRIVER(GPP_E7, 0, DEEP, - NONE), /* TPU_RST_PIN42 */ +/* CPU_GP1 */ PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TPU_RST_PIN42 */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* TP96 */ /* USB2_OCO# */ PAD_CFG_NC(GPP_E9), /* T1037 */ /* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* T1025 */