Attention is currently required from: Paul Menzel, Mario Scheithauer, Felix Held.
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69972 )
Change subject: mb/siemens/mc_ehl2: Disable GSPI2 controller ......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/69972/comment/886b1795_e7c035a6 PS2, Line 145: device pci 12.0 on end # GSPI2
looks like elkhartlake doesn't have a chipset devicetree that disables all non-essential devices by […]
It is basically this way: There is a FSP parameter array to let FSP enable or disable the three GSPI controllers. This parameter is processed before PCI enumerator is executed. A 0 in this parameter is equal to disable and because the devicetree does not utilize this parameters, they will be 0 per default. Therefore, FSP-S disable the PCI devices and coreboot can not just enable them. To have a device enabled, in addition the corresponding FSP parameter needs to be set accordingly (via devicetree parameter). So in other words: This device is not needed, it stayed in the devicetree as a 'left-over' from porting (from Intel's CRB) and we would like to remove it.