[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Jes Klinke (Code Review)]

Hello Jes Klinke,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/44359

to review the following change.

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
......................................................................

mainboard/google/volteer: Enable long cr50 ready pulses

For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.

A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided
that Cr50 firmware is new enough to support the register.

Change-Id: Idef1fffd410a345678da4b3c8aea46ac74a01470
Signed-off-by: Jes Bodi Klinke 
Bug: b:154333137
---
M src/mainboard/google/volteer/Kconfig
M src/mainboard/google/volteer/chromeos.c
M src/mainboard/google/volteer/variants/baseboard/devicetree.cb
3 files changed, 23 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44359/1

diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 82edb82..8eedca1 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -58,6 +58,10 @@
 config DRIVER_TPM_SPI_BUS
    default 0x1

+config CR50_USE_LONG_INTERRUPT_PULSES
+	bool
+	default y
+
 config MAINBOARD_DIR
    string
    default "google/volteer"
diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c
index abd50c5..8f43071 100644
--- a/src/mainboard/google/volteer/chromeos.c
+++ b/src/mainboard/google/volteer/chromeos.c
@@ -2,7 +2,10 @@

#include <baseboard/variants.h>
 #include <boot/coreboot_tables.h>
+#include <drivers/spi/tpm/tpm.h>
 #include <gpio.h>
+#include <security/tpm/tss.h>
+#include <soc/ramstage.h>
 #include <variant/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>

@@ -32,3 +35,18 @@
    gpios = variant_cros_gpios(&num);
    chromeos_acpi_gpio_generate(gpios, num);
 }
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	tlcl_lib_init();
+	if (get_cr50_board_cfg() & 0x01) {
+		printk(BIOS_INFO, "Enabling S0i3.4\n");
+	} else {
+		/* Disable S03.4, preventing the GPIO block from switching to
+		 * slow clock. */
+		printk(BIOS_INFO, "Not enabling S0i3.4\n");
+		params->LpmStateEnableMask &= ~0x80;
+	}
+}
+
+
diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
index 53bbe5a..6004c1d 100644
--- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb
@@ -203,6 +203,7 @@

# Enable S0ix
    register "s0ix_enable" = "1"
+	register "LpmStateEnableMask" = "0xFF"

# Enable DPTF
    register "dptf_enable" = "1"