Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39464 )
Change subject: mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3 ......................................................................
mb/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
Enbale CNVi in devicetree and add gpio pad configs for CNVi
BUG=none BRANCH=none TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: I71146960e0d53dae87946a0365dac6f224a72391 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c 2 files changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/39464/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb..a43011f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -130,7 +130,7 @@ device pci 0e.0 on end # VMD 0x9A0B
# From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 off end # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 30d148a..59ee5ff 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,6 +61,10 @@ PAD_CFG_GPO(GPP_C5, 1, PLTRST), PAD_CFG_GPI_APIC(GPP_C12, NONE, PLTRST, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */
+ /* CNVi */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + };
/* Early pad configuration in bootblock */