[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: add PcieRpAspm and PchPmPciePllSsc

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39330 )

Change subject: soc/intel/tigerlake: add PcieRpAspm and PchPmPciePllSsc
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39330/1/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39330/1/src/soc/intel/tigerlake/fsp... 
PS1, Line 48: /* Configure Aspm */
            : 	for (int i = 0; i < ARRAY_SIZE(config->PcieRpAspm); i++)
            : 		params->PcieRpAspm[i] = config->PcieRpAspm[i];
            : 
            : 	/* Configure Spread Spectrum */
            : 	params->PchPmPciePllSsc = config->PchPmPciePllSsc;
> There are some follow-up changes that get rid of these. […]

We don't need this change even for ES1. We can use it with FSP default