Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29156
Change subject: amd/stoneyridge/include/soc: GPIO control a mux base addresses double defined ......................................................................
amd/stoneyridge/include/soc: GPIO control a mux base addresses double defined
GPIO control a mux base addresses are defined within MMIO definitions and again bellow as GPIO specific base addresses. Eliminate those within MMIO bases.
BUG=b:117754420 TEST=Build grunt.
Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/acpi/gpio_lib.asl M src/soc/amd/stoneyridge/include/soc/iomap.h 2 files changed, 1 insertion(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29156/1
diff --git a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl index fbd6525..a2ea1ac 100644 --- a/src/soc/amd/stoneyridge/acpi/gpio_lib.asl +++ b/src/soc/amd/stoneyridge/acpi/gpio_lib.asl @@ -19,7 +19,7 @@ Method (GPAD, 0x1) { /* Arg0 - GPIO pin number */ - Return (Add(Multiply(Arg0, 4), GPIO_CONTROL_BASE)) + Return (Add(Multiply(Arg0, 4), AMD_GPIO_CONTROL)) }
/* Read pin control dword */ diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index beb2bc8..128318c 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -37,9 +37,7 @@ #define APU_SMI_BASE 0xfed80200 #define PM_MMIO_BASE 0xfed80300 #define BIOSRAM_MMIO_BASE 0xfed80500 -#define IOMUX_MMIO_BASE 0xfed80d00 #define MISC_MMIO_BASE 0xfed80e00 -#define GPIO_CONTROL_BASE 0xfed81500 #define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00 #define AOAC_MMIO_BASE 0xfed81e00