Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34424 )
Change subject: soc/amd/picasso: Update northbridge ......................................................................
Patch Set 15: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... File src/soc/amd/picasso/northbridge.c:
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 59: hybrid romstage Is the stack here?
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 63: DRAM consumed for hybrid romstage This is said twice here. Be more specific? hybrid romstage code?
https://review.coreboot.org/c/coreboot/+/34424/15/src/soc/amd/picasso/northb... PS15, Line 144: .read_resources = read_resources, Would you not want this to be part of a chip operation instead of a __pci_driver? It avoids needing to maintain a list of PCI ID's. With only one DID however it does not make all that much sense.