[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48281 )

Change subject: soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstage
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/48281/4/src/soc/intel/tigerlake/rom... 
PS4, Line 136: 	fsp_memory_init(s3wake);
             : 	pmc_set_disb();
             : 	if (!s3wake) {
             : 		if (CONFIG(SOC_INTEL_CSE_LITE_SKU))
             : 			cse_fw_sync();
> Is the MRC cache data written back to the SPI ROM before CSE FW Sync. […]

Yes, but if it runs before FSP-M in the first place, then there is no training on the first boot