[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Init SPI speeds & mode in psp_verstage

[Martin Roth (Code Review)]

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Eric Peers, Matt Papageorge,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43308

to look at the new patch set (#2).

Change subject: soc/amd/picasso: Init SPI speeds & mode in psp_verstage
......................................................................

soc/amd/picasso: Init SPI speeds & mode in psp_verstage

To make the SPI ROM reads as fast as possible for verstage verification,
we need to set up the SPI bus to read at the speeds we're using in the
rest of coreboot.

BUG=b:159811539
TEST=Build & boot. Verify that boot time decreases & that verstage
still passes.

Signed-off-by: Martin Roth 
Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc
---
M src/soc/amd/picasso/psp_verstage/fch.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43308/2