York Yang (york.yang@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11896
-gerrit
commit 35507e193c49cf55f2a6568eba71f64459df723a Author: York Yang york.yang@intel.com Date: Wed Oct 14 07:00:30 2015 -0700
intel/fsp_baytrail: Load BSP microcode in bootblock
Load microcode to BSP in bootblock so later on the FSP TempRamInit call can be success. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded a microcode before calling TempRamInit API, the call will fail with the error No Valid Microcode Was Found.
Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81 Signed-off-by: York Yang york.yang@intel.com --- src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 41b911e..a27901e 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -22,6 +22,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> +#include <cpu/intel/microcode/microcode.c> #include <baytrail/iosf.h> #include <baytrail/pci_devs.h> #include <baytrail/spi.h> @@ -116,9 +117,11 @@ static void set_up_lpc_pads(void)
static void bootblock_cpu_init(void) { - check_for_warm_reset();
+ /* Load microcode before any caching. */ + intel_update_microcode_from_cbfs(); + /* Allow memory-mapped PCI config access. */ setup_mmconfig(); enable_rom_caching();