[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Detect SOC before access ESPI register

[Bao Zheng (Code Review)]

Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/48842

to review the following change.

Change subject: soc/amd/common: Detect SOC before access ESPI register
......................................................................

soc/amd/common: Detect SOC before access ESPI register

Cezanne doesn't have eSPIx00034 register define in PPR.

Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/48842/1

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 0878fb7..ddeae98 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -824,6 +824,10 @@
 static void espi_setup_subtractive_decode(const struct espi_config *mb_cfg)
 {
    uint32_t global_ctrl_reg;
+
+	if (CONFIG(SOC_AMD_CEZANNE))
+		return;
+
    global_ctrl_reg = espi_read32(ESPI_GLOBAL_CONTROL_1);

if (mb_cfg->subtractive_decode) {